Datasheet > 74LVC16827APAG

74LVC16827APAG

更新时间： 2024-09-15 01:23:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
6页	104K
描述
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O

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74LVC16827APAG 数据手册

IDT74LVC16827A

3.3VCMOS20-BITBUFFERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

3.3V CMOS

IDT74LVC16827A

20-BIT BUFFER

WITH 5 VOLT TOLERANT I/O

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

This 20-bit buffer is built using advanced dual metal CMOS technology.

The LVC16827A provides high-performance bus interface buffering for

wide data/address paths or buses carrying parity. Two pairs of NAND-ed

outputenablecontrolsoffermaximumcontrolflexibilityandareorganized

tooperatethedeviceastwo10-bitbuffersorone20-bitbuffer. Flow-through

organization of signal pins simplifies layout. All inputs are designed with

hysteresis for improved noise margin.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

TheLVC16827Abufferisideallysuitedfordrivinghighcapacitanceloads

and low impedance backplanes.

• Available in TSSOP package

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of the device as a translator in a mixed 3.3V/5V supply system.

The LVC16827A has been designed with a ±24mA output driver. The

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

¹OE1

²OE1

1OE2

2OE2

1Y1

2Y1

1A1

2A1

TO NINE OTHER CHANNELS

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

AUGUST 2015

2015 Integrated Device Technology, Inc.

DSC-4489/6

12 3 4 5 6

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