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74LVC16374ADGG-Q1J PDF预览

74LVC16374ADGG-Q1J

更新时间： 2024-09-14 14:49:35
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
20页 141K
描述
74LVC(H)16374A-Q100 - 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state TSSOP 48-Pin

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74LVC16374ADGG-Q1J 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP包装说明：6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48
针数：48Reach Compliance Code：compliant
风险等级：5.79Base Number Matches：1

74LVC16374ADGG-Q1J 数据手册

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74LVC16374A; 74LVCH16374A  
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state  
Rev. 11 — 16 January 2013  
Product data sheet  
1. General description  
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring  
separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state  
outputs for bus-oriented applications. It consists of two sections of eight positive  
edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for  
each octal.  
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time  
requirements on the LOW-to-HIGH clock (CP) transition.  
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin  
nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE  
does not affect the state of the flip-flops.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and  
5 V applications.  
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused  
inputs.  
2. Features and benefits  
5 V tolerant inputs/outputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Multibyte flow-through standard pinout architecture  
Low inductance multiple supply pins for minimum noise and ground bounce  
Direct interface with TTL levels  
All data inputs have bus hold (74LVCH16374A only)  
High-impedance outputs when VCC = 0 V  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 
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