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74AUP1G02GN PDF预览

74AUP1G02GN

更新时间: 2024-09-22 11:11:15
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
18页 273K
描述
Low-power 2-input NOR gateProduction

74AUP1G02GN 数据手册

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74AUP1G02  
Low-power 2-input NOR gate  
Rev. 10.1 — 11 July 2023  
Product data sheet  
1. General description  
The 74AUP1G02 is a single 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit  
tolerant of slower input rise and fall times. This device ensures very low static and dynamic power  
consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for  
partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the  
potentially damaging backflow current through the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
CMOS low power dissipation  
High noise immunity  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Low static power consumption; ICC = 0.9 μA (maximum)  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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