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74AUP1G04GV,125 PDF预览

74AUP1G04GV,125

更新时间: 2024-01-17 05:07:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
22页 347K
描述
74AUP1G04 - Low-power inverter TSOP 5-Pin

74AUP1G04GV,125 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSOP包装说明:TSSOP, TSOP5/6,.11,37
针数:5Reach Compliance Code:compliant
风险等级:5.76系列:AUP/ULP/V
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2.9 mm负载电容(CL):30 pF
逻辑集成电路类型:INVERTER最大I(ol):0.0017 A
湿度敏感等级:1功能数量:1
输入次数:1端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:1.2/3.3 VProp。Delay @ Nom-Sup:16 ns
传播延迟(tpd):20.9 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.1 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL宽度:1.5 mm
Base Number Matches:1

74AUP1G04GV,125 数据手册

 浏览型号74AUP1G04GV,125的Datasheet PDF文件第2页浏览型号74AUP1G04GV,125的Datasheet PDF文件第3页浏览型号74AUP1G04GV,125的Datasheet PDF文件第4页浏览型号74AUP1G04GV,125的Datasheet PDF文件第5页浏览型号74AUP1G04GV,125的Datasheet PDF文件第6页浏览型号74AUP1G04GV,125的Datasheet PDF文件第7页 
74AUP1G04  
Low-power inverter  
Rev. 7 — 27 June 2012  
Product data sheet  
1. General description  
The 74AUP1G04 provides the single inverting buffer.  
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78B Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  
 
 

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