Datasheet > 74AUP1G04

74AUP1G04

更新时间： 2024-11-24 04:00:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		接口集成电路驱动
页数	文件大小	规格书
18页	397K
描述
Low power single inverter gate

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中文翻译

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74AUP1G04 数据手册

74AUP1G04

Low power single inverter gate

Features

■ High speed: t = 4.3 ns (max.) at V = 2.3 V

■ Power down protection on inputs and outputs

■ Balanced propagation delays:

t_PLH≈ t

PHL

■ Operating voltage range:

(opr) = 1.2 to 3.6 V

DFN6L

■ Low power dissipation:

= 1 µA (max.) at T = 85 °C

■ Latch-up performance exceeds 300 mA (JESD

78, Class II)

■ ESD performance:

SOT-665

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Applications

Description

■ Mobile phones

■ Personal digital assistants (PDAs)

The 74AUP1G04 is a low voltage CMOS single

inverter gate fabricated with sub-micron silicon

gate and double-layer metal wiring C MOS

technology. It is ideal for 1.2 to 3.6 V operations

and low power and low noise applications.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2kV ESD immunity and transient excess

voltage.

Table 1.

Device summary

Order code

Package

Packing

74AUPG04DTR

74AUPG04GTR

DFN6L (1.2 x 1 mm)

Tape and reel

SOT-665 (1.6 x 1.6 mm)

March 2008

Rev 1

1/18

www.st.com

12 3 4 5 6 7...18

中文翻译

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