Datasheet > 74AUP1G04GN

74AUP1G04GN

更新时间： 2024-11-25 06:22:11

品牌	Logo	应用领域
恩智浦 - NXP		栅输入元件光电二极管
页数	文件大小	规格书
21页	205K
描述
IC AUP/ULP/V SERIES, 1-INPUT INVERT GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6, Gate

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74AUP1G04GN 数据手册

74AUP1G04

Low-power inverter

Rev. 6 — 14 February 2012

Product data sheet

1. General description

The 74AUP1G04 provides the single inverting buffer.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78B Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial Power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...21

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