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74AUP1G04GV PDF预览

74AUP1G04GV

更新时间: 2024-11-25 11:10:47
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
20页 297K
描述
Low-power inverterProduction

74AUP1G04GV 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.58
系列:AUP/ULP/VJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2.9 mm
逻辑集成电路类型:INVERTER湿度敏感等级:1
功能数量:1输入次数:1
端子数量:5最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):20.9 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.1 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.5 mmBase Number Matches:1

74AUP1G04GV 数据手册

 浏览型号74AUP1G04GV的Datasheet PDF文件第2页浏览型号74AUP1G04GV的Datasheet PDF文件第3页浏览型号74AUP1G04GV的Datasheet PDF文件第4页浏览型号74AUP1G04GV的Datasheet PDF文件第5页浏览型号74AUP1G04GV的Datasheet PDF文件第6页浏览型号74AUP1G04GV的Datasheet PDF文件第7页 
74AUP1G04  
Low-power inverter  
Rev. 12.1 — 11 July 2023  
Product data sheet  
1. General description  
The 74AUP1G04 is a single inverter.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times  
across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire VCC range  
from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
CMOS low power dissipation  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78B Class II  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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