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74AHCT273D,118 PDF预览

74AHCT273D,118

更新时间: 2024-11-27 19:45:39
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
18页 95K
描述
74AHC(T)273 - Octal D-type flip-flop with reset; positive-edge trigger SOP 20-Pin

74AHCT273D,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.33
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:45000000 Hz最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):11.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:65 MHzBase Number Matches:1

74AHCT273D,118 数据手册

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74AHC273; 74AHCT273  
Octal D-type flip-flop with reset; positive-edge trigger  
Rev. 03 — 13 May 2008  
Product data sheet  
1. General description  
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D  
inputs and Q outputs.  
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops  
simultaneously.  
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is  
transferred to the corresponding output (Qn) of the flip-flop.  
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR  
input.  
The device is useful for applications where only the true output is required and the clock  
and master reset are common to all storage elements.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Ideal buffer for MOS microcontroller or memory  
I Common clock and master reset  
I Related product versions:  
N 74AHC377; 74AHCT377 for clock enable version  
N 74AHC373; 74AHCT373 for transparent latch version  
N 74AHC374; 74AHCT374 for 3-state version  
I Input levels:  
N For 74AHC273: CMOS level  
N For 74AHCT273: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

74AHCT273D,118 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT273DW TI

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OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SN74AHC273DW TI

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OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SN74HC273NSR TI

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OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

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