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74AHCT273PW-T PDF预览

74AHCT273PW-T

更新时间: 2024-11-27 12:59:55
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
18页 111K
描述
IC AHCT/VHCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20, FF/Latch

74AHCT273PW-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.09系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:45000000 Hz
最大I(ol):0.008 A湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:65 MHz
Base Number Matches:1

74AHCT273PW-T 数据手册

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74AHC273; 74AHCT273  
Octal D-type flip-flop with reset; positive-edge trigger  
Rev. 03 — 13 May 2008  
Product data sheet  
1. General description  
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D  
inputs and Q outputs.  
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops  
simultaneously.  
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is  
transferred to the corresponding output (Qn) of the flip-flop.  
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR  
input.  
The device is useful for applications where only the true output is required and the clock  
and master reset are common to all storage elements.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Ideal buffer for MOS microcontroller or memory  
I Common clock and master reset  
I Related product versions:  
N 74AHC377; 74AHCT377 for clock enable version  
N 74AHC373; 74AHCT373 for transparent latch version  
N 74AHC374; 74AHCT374 for 3-state version  
I Input levels:  
N For 74AHC273: CMOS level  
N For 74AHCT273: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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