Datasheet > 74AHCT2G

74AHCT2G

更新时间： 2024-11-26 22:56:15

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	83K
描述
Dual 2-input OR gate

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中文翻译

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数据手册

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74AHCT2G 数据手册

74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

Rev. 01 — 23 February 2004

Product data sheet

1. General description

The 74AHC2G/AHCT2G32 is a high-speed Si-gate CMOS device. This device provides

two 2-input OR gates.

2. Features

■ Symmetrical output impedance

■ High noise immunity

■ ESD protection:

◆ HBM EIA/JESD22-A114-A exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

◆ CDM EIA/JESD22-C101 exceeds 1000 V.

■ Low power dissipation

■ Balanced propagation delays

■ SOT505-2 and SOT765-1 package

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T_amb= 25 °C; t_r= t_f≤ 3.0 ns.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Type 74AHC2G

t_PHL, t_PLH

propagation delay C_L= 15 pF;

3.2

5.5

nA and nB to nY

V_CC= 5 V

C_I

input capacitance

1.5

[1] [2]

C_PD

power dissipation C_L= 50 pF;

capacitance f_i= 1 MHz

Type 74AHCT2G

t_PHL, t_PLH

propagation delay C_L= 15 pF;

3.3

6.9

nA and nB to nY

V_CC= 5 V

C_I

input capacitance

1.5

[1] [2]

C_PD

power dissipation C_L= 50 pF;

capacitance f_i= 1 MHz

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

12 3 4 5 6 7...16

中文翻译

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