Datasheet > 74AHCT273-Q100

74AHCT273-Q100

更新时间： 2024-09-19 01:09:51

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	814K
描述
Octal D-type flip-flop with reset; positive-edge trigger

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AHCT273-Q100 数据手册

74AHC273-Q100;

74AHCT273-Q100

Octal D-type flip-flop with reset; positive-edge trigger

Rev. 1 — 27 March 2013

Product data sheet

1. General description

The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7-A.

The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with

individual D inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops

simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding output (Qn) of the flip-flop.

All outputs are forced LOW, independent of clock or data inputs, by a LOW on the MR

input.

The device is useful for applications where only the true output is required and the clock

and master reset are common to all storage elements.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Balanced propagation delays

 All inputs have Schmitt-trigger actions

 Inputs accept voltages higher than V_CC

 Ideal buffer for MOS microcontroller or memory

 Common clock and master reset

 Input levels:

 For 74AHC273-Q100: CMOS level

 For 74AHCT273-Q100: TTL level

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...19

中文翻译

下载PDF

与74AHCT273-Q100相关器件

型号	品牌	获取价格	描述	数据表
74AHCT2G	NXP	获取价格	Dual 2-input OR gate
74AHCT2G00	NXP	获取价格	Dual 2-input NAND gate
74AHCT2G00DC	NXP	获取价格	The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device
74AHCT2G00DC	NEXPERIA	获取价格	Dual 2-input NAND gateProduction
74AHCT2G00DC,125	NXP	获取价格	74AHC(T)2G00 - Dual 2-input NAND gate SSOP 8-Pin
74AHCT2G00DC-Q100	NXP	获取价格	AHCT/VHCT/VT SERIES, DUAL 2-INPUT NAND GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VS
74AHCT2G00DC-Q100	NEXPERIA	获取价格	Dual 2-input NAND gate
74AHCT2G00DC-Q100,125	NXP	获取价格	NAND Gate, AHCT/VHCT/VT Series, 2-Func, 2-Input, CMOS, PDSO8
74AHCT2G00DP	NXP	获取价格	The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device
74AHCT2G00DP-Q100	NXP	获取价格	AHCT/VHCT/VT SERIES, DUAL 2-INPUT NAND GATE, PDSO8, 3 MM, PLASTIC, SOT505-2, TSSOP-8