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71V546S133PFG8 PDF预览

71V546S133PFG8

更新时间： 2024-11-24 00:59:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 228K
描述
Synchronous SRAM with ZBT Feature Burst Counter and Pipelined Outputs

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中文翻译

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71V546S133PFG8 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TQFP
包装说明：QFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.2
最长访问时间：4.2 ns最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
Base Number Matches：1

71V546S133PFG8 数据手册

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128K x 36, 3.3V Synchronous  
SRAM with ZBTFeature  
Burst Counter and Pipelined Outputs  
IDT71V546S  
Features  
128K x 36 memory configuration, pipelined outputs  
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply ( 5%)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized registered outputs eliminate the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Packaged in a JEDEC standard 100-pin TQFP package  
Green parts available, see Ordering Information  
Functional Block Diagram  
128K x 36 BIT  
MEMORY ARRAY  
LBO  
Address A [0:16]  
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
D
Control  
CEN  
ADV/LD  
DI  
DO  
BWx  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Output Register  
Q
Clock  
Gate  
OE  
3821 drw 01  
.
Data I/O [0:31], I/O P[1:4]  
AUGUST 2017  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
1
DSC-3821/07  
©2017 Integrated Device Technology, Inc.  
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71V546S133PFG8 替代型号

型号 品牌 替代类型 描述 数据表
71V2556S133PFG IDT

完全替代

 3.3V Synchronous ZBT SRAMs
71V546S133PFG IDT

完全替代

 128K x 36, 3.3V Synchronous SRAM with ZBT™

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