Datasheet > 71V547S85PFI

71V547S85PFI

更新时间： 2024-11-20 07:16:43

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
19页	1363K
描述
ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100

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71V547S85PFI 数据手册

128K X 36, 3.3V Synchronous IDT71V547S/XS

SRAM with ZBT™ Feature, Burst

Counter and Flow-Through Outputs

Features

◆

128K x 36 memory configuration, flow-through outputs

Supports high performance system speed - 95 MHz

(8ns Clock-to-Data Access)

TheIDT71V547containsaddress,data-inandcontrolsignalregisters.

Theoutputsareflow-through(nooutputdataregister).Outputenableis

theonlyasynchronoussignalandcanbeusedtodisabletheoutputsat

anygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V547 to

be suspended as long as necessary. All synchronous inputs are

ignored when CEN is high and the internal device registers will hold

their previous values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive

whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany

burstinprogressisstopped.However,anypendingdatatransfers(reads

orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe

chipwasdeselectedorwriteinitiated.

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized signal eliminates the need to

control OE

◆

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

Packaged in a JEDEC standard 100-pin TQFP package

TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the

IDT71V547canprovidefourcyclesofdataforasingleaddresspresented

totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput

pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW)orincrementtheinternalburstcounter(ADV/LD=HIGH).

TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.

Description

The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate

deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,

orwritesandreads.ThusithasbeengiventhenameZBT^TM,orZeroBus

Turn-around.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit

read or write.

PinDescriptionSummary

- A16

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Three Chip Enables

Output Enable

, CE

2, CE

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

3.3V Power

Synchronous

Static

LBO

- I/O31, I/OP1

I/O^P4

I/O

Synchronous

Static

Supply

VSS

Ground

Static

3822 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

OCTOBER 2008

DSC-3822/04

12 3 4 5 6 7...19

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与71V547S85PFI相关器件

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71V547S90PFG	IDT	获取价格	Synchronous SRAM
71V547S90PFG8	IDT	获取价格	Synchronous SRAM
71V547S90PFGI	IDT	获取价格	Synchronous SRAM
71V547S90PFGI8	IDT	获取价格	Synchronous SRAM
71V632S5PF	IDT	获取价格	3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect
71V632S5PFGI71V632S5	IDT	获取价格	Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100
71V632S6PF	IDT	获取价格	Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
71V632S6PF8	IDT	获取价格	Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
71V632S6PFG	ROCHESTER	获取价格	64KX32 CACHE SRAM, 6ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
71V632S6PFG71V632S6	IDT	获取价格	Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100

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