5秒后页面跳转
捷配首页

Datasheet > 71V546S133PFGI
71V546S133PFGI PDF预览

71V546S133PFGI

更新时间： 2024-11-20 00:52:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 164K
描述
3.3V Synchronous SRAM

阅读下载

中文翻译

获取价格

71V546S133PFGI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TQFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.17
最长访问时间：4.2 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.045 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.31 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

71V546S133PFGI 数据手册

 浏览型号71V546S133PFGI的Datasheet PDF文件第2页浏览型号71V546S133PFGI的Datasheet PDF文件第3页浏览型号71V546S133PFGI的Datasheet PDF文件第4页浏览型号71V546S133PFGI的Datasheet PDF文件第5页浏览型号71V546S133PFGI的Datasheet PDF文件第6页浏览型号71V546S133PFGI的Datasheet PDF文件第7页 
128K x 36, 3.3V Synchronous IDT71V546S/XS  
SRAM with ZBT™ Feature,  
Burst Counter and Pipelined Outputs  
Features  
◆
128K x 36 memory configuration, pipelined outputs  
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
clock cycle, and two cycles later its associated data cycle occurs, be it  
read or write.  
TheIDT71V546containsdataI/O,addressandcontrolsignalregis-  
ters. Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be  
suspended as long as necessary. All synchronous inputs are ignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive  
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany  
burst that was in progress is stopped. However, any pending data  
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo  
cyclesafterthechipisdeselectedorawriteinitiated.  
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized registered outputs eliminate the  
need to control OE  
◆
◆
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin TQFP package  
TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the  
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented  
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput  
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.  
The ADV/LD signal is used to load a new external address (ADV/LD =  
LOW) or increment the internal burst counter (ADV/LD = HIGH).  
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.  
Description  
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAM organized as 128K x 36 bits. It is designed to  
eliminatedeadbuscycleswhenturningthebusaroundbetweenreads  
andwrites,orwritesandreads. ThusithasbeengiventhenameZBTTM,  
or Zero Bus Turn-around.  
Address and control signals are applied to the SRAM during one  
PinDescriptionSummary  
A
0
- A16  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Three Chip Enables  
Output Enable  
CE1  
, CE  
2
, CE  
2
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
Advance Burst Address / Load New Address  
Linear / Interleaved Burst Order  
Data Input/Output  
Synchronous  
Static  
LBO  
I/O0  
- I/O31, I/OP1 - I/OP4  
Synchronous  
Static  
V
DD  
SS  
3.3V Power  
Supply  
Supply  
V
Ground  
Static  
3821 tbl 01  
OCTOBER 2008  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
1
DSC-3821/05  
©2008 Integrated Device Technology, Inc.  
1234567...21

中文翻译

下载PDF

71V546S133PFGI 替代型号

型号 品牌 替代类型 描述 数据表
71V2556S133PFGI IDT

完全替代

 3.3V Synchronous ZBT SRAMs

与71V546S133PFGI相关器件

型号 品牌 获取价格 描述 数据表
71V546S133PFGI8 IDT

获取价格

 		Synchronous SRAM with ZBT Feature Burst Counter and Pipelined Outputs
71V546XS100PFG IDT

获取价格

 		3.3V Synchronous SRAM
71V546XS100PFGI IDT

获取价格

 		3.3V Synchronous SRAM
71V546XS117PFG IDT

获取价格

 		3.3V Synchronous SRAM
71V546XS117PFGI IDT

获取价格

 		3.3V Synchronous SRAM
71V546XS133PFG IDT

获取价格

 		3.3V Synchronous SRAM
71V546XS133PFGI IDT

获取价格

 		3.3V Synchronous SRAM
71V547 RENESAS

获取价格

 		3.3V 128K x 36 ZBT Synchronous Flow-Through SRAM
71V547S100PFG IDT

获取价格

 		Synchronous SRAM
71V547S100PFG8 IDT

获取价格

 		Synchronous SRAM

与71V546S133PFGI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证