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71V546S133PFG

更新时间： 2024-11-19 12:52:35
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器PC时钟
页数 文件大小 规格书
21页 1003K
描述
128K x 36, 3.3V Synchronous SRAM with ZBT™ Feature, Burst Counter and Pipelined Outputs

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71V546S133PFG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TQFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：1.35
Samacsys Confidence：3Samacsys Status：Released
Samacsys PartID：11321557Samacsys Pin Count：100
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Quad Flat Packages
Samacsys Footprint Name：100-Pin Plastic Thin Quad Flatpack (PKG100)Samacsys Released Date：2020-01-30 06:39:34
Is Samacsys：N最长访问时间：4.2 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

71V546S133PFG 数据手册

 浏览型号71V546S133PFG的Datasheet PDF文件第2页浏览型号71V546S133PFG的Datasheet PDF文件第3页浏览型号71V546S133PFG的Datasheet PDF文件第4页浏览型号71V546S133PFG的Datasheet PDF文件第5页浏览型号71V546S133PFG的Datasheet PDF文件第6页浏览型号71V546S133PFG的Datasheet PDF文件第7页 
128K x 36, 3.3V Synchronous IDT71V546S/XS  
SRAM with ZBT™ Feature,  
Burst Counter and Pipelined Outputs  
Features  
◆
128K x 36 memory configuration, pipelined outputs  
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
clockcycle,andtwocycles laterits associateddatacycleoccurs,beit  
read or write.  
TheIDT71V546containsdataI/O,addressandcontrolsignalregis-  
ters. Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
AClockEnable (CEN)pinallows operationofthe IDT71V546tobe  
suspended as long as necessary. All synchronous inputs are ignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive  
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany  
burst that was in progress is stopped. However, any pending data  
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo  
cyclesafterthechipisdeselectedorawriteinitiated.  
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized registered outputs eliminate the  
need to control OE  
◆
◆
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin TQFP package  
TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the  
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented  
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput  
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.  
The ADV/LD signalis usedtoloada newexternaladdress (ADV/LD =  
LOW) orincrementtheinternalburstcounter(ADV/LD =HIGH).  
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.  
Description  
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAM organized as 128K x 36 bits. It is designed to  
eliminatedeadbuscycleswhenturningthebusaroundbetweenreads  
TM  
andwrites,orwritesandreads. ThusithasbeengiventhenameZBT ,  
or Zero Bus Turn-around.  
Address and control signals are applied to the SRAM during one  
PinDescriptionSummary  
A0  
- A16  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Three Chip Enables  
Output Enable  
CE1  
, CE  
2
, CE  
2
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
Advance Burst Address / Load New Address  
Linear / Interleaved Burst Order  
Data Input/Output  
Synchronous  
Static  
LBO  
I/O0  
- I/O31, I/OP1 - I/OP4  
Synchronous  
Static  
VDD  
3.3V Power  
Supply  
Supply  
VSS  
Ground  
Static  
3821 tbl 01  
OCTOBER 2008  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
1
DSC-3821/05  
©2007IntegratedDeviceTechnology,Inc.  
1234567...21

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71V546S133PFG 替代型号

型号 品牌 替代类型 描述 数据表
71V2556S133PFG8 IDT

完全替代

 3.3V Synchronous ZBT SRAMs
71V2556S133PFG IDT

完全替代

 3.3V Synchronous ZBT SRAMs

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