128K X 36, 3.3V Synchronous
71V547S
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
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Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
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128K x 36 memory configuration, flow-through outputs
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
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ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized signal eliminates the need to
control OE
Packaged in a JEDEC standard 100-pin TQFP package
FunctionalBlockDiagram
128K x 36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
Control
CEN
ADV/LD
DI
DO
BWx
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
,
Data I/O [0:31], I/O P[1:4]
3822 drw 01
ZBT and Zero Bus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc.
1
Apr.24.20