128K X 36, 3.3V Synchronous IDT71V547S/XS
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
◆
128K x 36 memory configuration, flow-through outputs
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
TheIDT71V547containsaddress,data-inandcontrolsignalregisters.
Theoutputsareflow-through(nooutputdataregister).Outputenableis
theonlyasynchronoussignalandcanbeusedtodisabletheoutputsat
anygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold
their previous values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany
burstinprogressisstopped.However,anypendingdatatransfers(reads
orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe
chipwasdeselectedorwriteinitiated.
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized signal eliminates the need to
control OE
◆
◆
◆
◆
◆
◆
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the
IDT71V547canprovidefourcyclesofdataforasingleaddresspresented
totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW)orincrementtheinternalburstcounter(ADV/LD=HIGH).
TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,
orwritesandreads.ThusithasbeengiventhenameZBTTM,orZeroBus
Turn-around.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit
read or write.
PinDescriptionSummary
A
0
- A16
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Three Chip Enables
Output Enable
CE
1
, CE
2, CE
2
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Synchronous
Static
LBO
- I/O31, I/OP1
I/OP4
I/O
0
-
Synchronous
Static
V
DD
Supply
Supply
VSS
Ground
Static
3822 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
OCTOBER 2008
1
DSC-3822/04
©2007IntegratedDeviceTechnology,Inc.