Datasheet > 71V632S5PFGI71V632S5

71V632S5PFGI71V632S5

更新时间： 2023-01-02 20:38:26

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
19页	308K
描述
Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100

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71V632S5PFGI71V632S5 数据手册

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64K x 32

3.3VSynchronousSRAM

PipelinedOutputs

IDT71V632/Z

BurstCounter,SingleCycleDeselect

Features

withfullsupportofthePentium™andPowerPC™processorinterfaces.

Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-

ary cache performance for processors up to 117MHz.

The IDT71V632 SRAM contains write, data, address, and control

registers. InternallogicallowstheSRAMtogenerateaself-timedwrite

baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite

cycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

system designer, as the IDT71V632 can provide four cycles of data for

asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter

acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess

sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore

it is available on the next rising clock edge. If burst mode operation is

selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe

availabletotheuseronthenextthreerisingclockedges.Theorderofthese

threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO

inputpin.

◆

64K x 32 memory configuration

◆

Supports high system speed:

Commercial:

– A4 4.5ns clock access time (117 MHz)

CommercialandIndustrial:

– 5 5ns clock access time (100 MHz)

– 6 6ns clock access time (83 MHz)

– 7 7ns clock access time (66 MHz)

◆

Single-cycle deselect functionality (Compatible with

Micron Part # MT58LC64K32D7LG-XX)

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

◆

write enable (BWE), and byte writes (BWx)

Power down controlled by ZZ input

Operates with a single 3.3V power supply (+10/-5%)

Packaged in a JEDEC Standard 100-pin rectangular plastic

◆

thin quad flatpack (TQFP).

TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity

inbothdesktopandnotebookapplications.

Description

TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32

PinDescriptionSummary

–A15

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

0, CS

Chips Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW1, BW2, BW3, BW

CLK

ADV

ADSC

ADSP

LBO

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Asynchronous

Synchronous

N/A

I/O

–I/O31

DD, VDDQ

SS, VSSQ

Data Input/Output

3.3V

Power

Array Ground, I/O Ground

N/A

3619 tbl 01

PentiumprocessorisatrademarkofIntelCorp.

PowerPCisatrademarkofInternationalBusinessMachines,Inc.

MAY 2010

DSC-3619/07

12 3 4 5 6 7...19

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与71V632S5PFGI71V632S5相关器件

型号	品牌	描述	获取价格	数据表
71V632S6PF	IDT	Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
71V632S6PF8	IDT	Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
71V632S6PFG	ROCHESTER	64KX32 CACHE SRAM, 6ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
71V632S6PFG71V632S6	IDT	Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100	获取价格
71V632S6PFI	IDT	Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
71V632S6PFI8	IDT	Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格

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