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71V546XS117PFGI PDF预览

71V546XS117PFGI

更新时间： 2024-01-01 02:20:36
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 164K
描述
3.3V Synchronous SRAM

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71V546XS117PFGI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：QFP, QFP100,.63X.87
Reach Compliance Code：compliant风险等级：5.56
最长访问时间：4.5 ns最大时钟频率 (fCLK)：117 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大待机电流：0.045 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.285 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
Base Number Matches：1

71V546XS117PFGI 数据手册

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128K x 36, 3.3V Synchronous IDT71V546S/XS  
SRAM with ZBT™ Feature,  
Burst Counter and Pipelined Outputs  
Features  
◆
128K x 36 memory configuration, pipelined outputs  
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
clock cycle, and two cycles later its associated data cycle occurs, be it  
read or write.  
TheIDT71V546containsdataI/O,addressandcontrolsignalregis-  
ters. Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be  
suspended as long as necessary. All synchronous inputs are ignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive  
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany  
burst that was in progress is stopped. However, any pending data  
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo  
cyclesafterthechipisdeselectedorawriteinitiated.  
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized registered outputs eliminate the  
need to control OE  
◆
◆
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin TQFP package  
TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the  
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented  
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput  
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.  
The ADV/LD signal is used to load a new external address (ADV/LD =  
LOW) or increment the internal burst counter (ADV/LD = HIGH).  
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.  
Description  
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAM organized as 128K x 36 bits. It is designed to  
eliminatedeadbuscycleswhenturningthebusaroundbetweenreads  
andwrites,orwritesandreads. ThusithasbeengiventhenameZBTTM,  
or Zero Bus Turn-around.  
Address and control signals are applied to the SRAM during one  
PinDescriptionSummary  
A
0
- A16  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Three Chip Enables  
Output Enable  
CE1  
, CE  
2
, CE  
2
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
Advance Burst Address / Load New Address  
Linear / Interleaved Burst Order  
Data Input/Output  
Synchronous  
Static  
LBO  
I/O0  
- I/O31, I/OP1 - I/OP4  
Synchronous  
Static  
V
DD  
SS  
3.3V Power  
Supply  
Supply  
V
Ground  
Static  
3821 tbl 01  
OCTOBER 2008  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
1
DSC-3821/05  
©2008 Integrated Device Technology, Inc.  
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