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71V547S90PFGI8 PDF预览

71V547S90PFGI8

更新时间: 2024-11-24 00:47:31
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
20页 711K
描述
Synchronous SRAM

71V547S90PFGI8 数据手册

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128K X 36, 3.3V Synchronous IDT71V547S/XS  
SRAM with ZBT™ Feature, Burst  
Counter and Flow-Through Outputs  
Features  
Single R/W (READ/WRITE) control pin  
128K x 36 memory configuration, flow-through outputs  
Supports high performance system speed - 95 MHz  
(8ns Clock-to-Data Access)  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Packaged in a JEDEC standard 100-pin TQFP package  
Internally synchronized signal eliminates the need to  
control OE  
FunctionalBlockDiagram  
128K x 36 BIT  
MEMORY ARRAY  
LBO  
Address A [0:16]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
Control  
CEN  
ADV/LD  
DI  
DO  
BWx  
D
Q
Control Logic  
Clk  
Mux  
Sel  
Clock  
Gate  
OE  
,
Data I/O [0:31], I/O P[1:4]  
3822 drw 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
FEBRUARY 2015  
1
DSC-3822/07  
©2015 Integrated Device Technology, Inc.  

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