Datasheet > 71V547S90PFGI8

71V547S90PFGI8

更新时间： 2022-02-26 09:14:35

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
20页	711K
描述
Synchronous SRAM

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数据手册

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71V547S90PFGI8 数据手册

IDT71V547, 128K x 36, 3.3V Synchronous SRAM with

ZBT Feature, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive

whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany

burstinprogressisstopped.However,anypendingdatatransfers(reads

orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe

chipwasdeselectedorwriteinitiated.

Description

The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate

deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,

orwritesandreads.ThusithasbeengiventhenameZBT^TM,orZeroBus

Turn-around.

TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the

IDT71V547canprovidefourcyclesofdataforasingleaddresspresented

totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput

pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW) or increment the internal burst counter (ADV/LD = HIGH).

TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit

read or write.

The IDT71V547 contains address, data-in and control signal regis-

ters. Theoutputsareflow-through(nooutputdataregister).Outputenable

istheonlyasynchronoussignalandcanbeusedtodisabletheoutputsat

anygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V547 to

be suspended as long as necessary. All synchronous inputs are

ignored when CEN is high and the internal device registers will hold

their previous values.

PinDescriptionSummary

- A16

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Three Chip Enables

Output Enable

, CE

2, CE

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

3, BW

CLK

ADV/LD

LBO

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

Synchronous

Static

I/O0

- I/O31, I/OP1 - I/OP4

Synchronous

Static

3.3V Power

Supply

Ground

Static

3822 tbl 01

123 4 5 6 7...20

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