Datasheet > 71V547S90PFGI8

71V547S90PFGI8

更新时间： 2022-02-26 09:14:35

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
20页	711K
描述
Synchronous SRAM

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数据手册

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71V547S90PFGI8 数据手册

IDT71V547, 128K x 36, 3.3V Synchronous SRAM with

ZBT Feature, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

3822 tbl 09

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

3822 tbl 10

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

FunctionalTimingDiagram⁽¹⁾

n+37

CYCLE

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

CLOCK

(2)

ADDRESS

A29

C29

A30

C30

A31

C31

A32

C32

A33

C33

A34

C34

A35

C35

A36

C36

A37

C37

(A0 - A16)

CONTROL

(R/W, ADV/LD, BWx)

(2)

DATA

D/Q28

D/Q29

D/Q30

D/Q31

D/Q32

D/Q33

D/Q34

D/Q35

D/Q36

I/O [0:31], I/O P[1:4]

3822 drw 03

NOTE:

1. This assumes CEN, CE1, CE2 and CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.42

1...4 5 678 9 10...20

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