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71V632S7PFGI71V632S7 PDF预览

71V632S7PFGI71V632S7

更新时间: 2024-01-05 18:47:54
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 308K
描述
Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100

71V632S7PFGI71V632S7 技术参数

生命周期:Active零件包装代码:QFP
包装说明:20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100针数:100
Reach Compliance Code:compliant风险等级:5.8
JESD-30 代码:R-PQFP-G100内存集成电路类型:CACHE SRAM
端子数量:100封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:FLATPACK
表面贴装:YES端子形式:GULL WING
端子位置:QUADBase Number Matches:1

71V632S7PFGI71V632S7 数据手册

 浏览型号71V632S7PFGI71V632S7的Datasheet PDF文件第2页浏览型号71V632S7PFGI71V632S7的Datasheet PDF文件第3页浏览型号71V632S7PFGI71V632S7的Datasheet PDF文件第4页浏览型号71V632S7PFGI71V632S7的Datasheet PDF文件第5页浏览型号71V632S7PFGI71V632S7的Datasheet PDF文件第6页浏览型号71V632S7PFGI71V632S7的Datasheet PDF文件第7页 
64K x 32  
3.3VSynchronousSRAM  
PipelinedOutputs  
IDT71V632/Z  
BurstCounter,SingleCycleDeselect  
Features  
withfullsupportofthePentiumandPowerPCprocessorinterfaces.  
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-  
ary cache performance for processors up to 117MHz.  
The IDT71V632 SRAM contains write, data, address, and control  
registers. InternallogicallowstheSRAMtogenerateaself-timedwrite  
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite  
cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
system designer, as the IDT71V632 can provide four cycles of data for  
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter  
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess  
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore  
it is available on the next rising clock edge. If burst mode operation is  
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe  
availabletotheuseronthenextthreerisingclockedges.Theorderofthese  
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO  
inputpin.  
64K x 32 memory configuration  
Supports high system speed:  
Commercial:  
– A4 4.5ns clock access time (117 MHz)  
CommercialandIndustrial:  
– 5 5ns clock access time (100 MHz)  
– 6 6ns clock access time (83 MHz)  
– 7 7ns clock access time (66 MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC64K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity  
inbothdesktopandnotebookapplications.  
Description  
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32  
PinDescriptionSummary  
A
0
A15  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0, CS  
1
Chips Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW1, BW2, BW3, BW  
4
CLK  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
Asynchronous  
Synchronous  
N/A  
I/O  
0
–I/O31  
DD, VDDQ  
SS, VSSQ  
Data Input/Output  
V
3.3V  
Power  
Power  
V
Array Ground, I/O Ground  
N/A  
3619 tbl 01  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
MAY 2010  
1
©2010IntegratedDeviceTechnology,Inc.  
DSC-3619/07  

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