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71V632ZS7PFG PDF预览

71V632ZS7PFG

更新时间: 2024-11-26 18:55:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
19页 308K
描述
Standard SRAM, 64KX32, 7ns, CMOS, PQFP100

71V632ZS7PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LQFP, QFP100,.63X.87
Reach Compliance Code:compliant风险等级:5.56
最长访问时间:7 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):66 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:32
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.01 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.16 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

71V632ZS7PFG 数据手册

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64K x 32  
3.3VSynchronousSRAM  
PipelinedOutputs  
IDT71V632/Z  
BurstCounter,SingleCycleDeselect  
Features  
withfullsupportofthePentiumandPowerPCprocessorinterfaces.  
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-  
ary cache performance for processors up to 117MHz.  
The IDT71V632 SRAM contains write, data, address, and control  
registers. InternallogicallowstheSRAMtogenerateaself-timedwrite  
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite  
cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
system designer, as the IDT71V632 can provide four cycles of data for  
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter  
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess  
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore  
it is available on the next rising clock edge. If burst mode operation is  
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe  
availabletotheuseronthenextthreerisingclockedges.Theorderofthese  
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO  
inputpin.  
64K x 32 memory configuration  
Supports high system speed:  
Commercial:  
– A4 4.5ns clock access time (117 MHz)  
CommercialandIndustrial:  
– 5 5ns clock access time (100 MHz)  
– 6 6ns clock access time (83 MHz)  
– 7 7ns clock access time (66 MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC64K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity  
inbothdesktopandnotebookapplications.  
Description  
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32  
PinDescriptionSummary  
A
0
A15  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0, CS  
1
Chips Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW1, BW2, BW3, BW  
4
CLK  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
Asynchronous  
Synchronous  
N/A  
I/O  
0
–I/O31  
DD, VDDQ  
SS, VSSQ  
Data Input/Output  
V
3.3V  
Power  
Power  
V
Array Ground, I/O Ground  
N/A  
3619 tbl 01  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
MAY 2010  
1
©2010IntegratedDeviceTechnology,Inc.  
DSC-3619/07  

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