Datasheet > 71V632S7PFGI71V632S7

71V632S7PFGI71V632S7

更新时间： 2024-01-01 20:37:15

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
19页	308K
描述
Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100

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71V632S7PFGI71V632S7 技术参数

生命周期：	Active	零件包装代码：	QFP
包装说明：	20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100	针数：	100
Reach Compliance Code：	compliant	风险等级：	5.8
JESD-30 代码：	R-PQFP-G100	内存集成电路类型：	CACHE SRAM
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	FLATPACK
表面贴装：	YES	端子形式：	GULL WING
端子位置：	QUAD	Base Number Matches：	1

71V632S7PFGI71V632S7 数据手册

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IDT71V632, 64K x 32, 3.3V Synchronous SRAM

with Pipelined Outputs and Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Symbol

Rating

Value

Unit

Grade

Temperature

0°C to +70°C

–40°C to +85°C

VDDQ

(2)

Terminal Voltage with

Respect to GND

–0.5 to +4.6

TERM

Commercial

Industrial

3.3V+10/-5% 3.3V+10/-5%

(3)

TERM

Terminal Voltage with

Respect to GND

–0.5 to VDD+0.5

3.3V+10/-5% 3.3V+10/-5%

3619 tbl 03

Operating Temperature

Temperature Under Bias

Storage Temperature

Power Dissipation

0 to +70

–55 to +125

1.0

^oC

BIAS

STG

RecommendedDCOperating

Conditions

OUT

DC Output Current

Symbol

Parameter

Min.

3.135

Max.

3.63

Unit

3619 tbl 05

DDQ

SS,

Core Supply Voltage

I/O Supply Voltage

Ground

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD, VDDQ and Input terminals only.

VSSQ

Input High Voltage — Inputs

Input High Voltage — I/O

Input Low Voltage

2.0

5.0⁽¹⁾

2.0

DDQ+0.3⁽²⁾

3. I/O terminals.

–0.3⁽³⁾

0.8

3619 tbl 04

NOTES:

1. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.

Capacitance

(TA = +25°C, f = 1.0MHz, TQFP package)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

CIN

CI/O

3619 tbl 06

NOTE:

1. This parameter is guaranteed by device characterization, but not production

tested.

6.42

1 2 345 6 7...19

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与71V632S7PFGI71V632S7相关器件

型号	品牌	描述	获取价格	数据表
71V632S7PFI8	IDT	Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
71V632SA4PF	IDT	3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect	获取价格
71V632SA4PFG	IDT	Standard SRAM, 64KX32, 4.5ns, CMOS, PQFP100	获取价格
71V632SA4PFG71V632SA4	IDT	Cache SRAM, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-136DJ, TQFP-100	获取价格
71V632ZS5PF8	IDT	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQF	获取价格
71V632ZS5PFG	IDT	Standard SRAM, 64KX32, 5ns, CMOS, PQFP100	获取价格

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