IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
Address Inputs
I
N/A
A0 - A16
Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK, ADV/LD Low, CEN Low and true chip enables.
Address/Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new
address and control when it is sampled low at the rising edge of clock with the
chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
ADV/LD
R/W
Read/Write
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place one clock cycle later.
Clock Enable
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of CEN sampled high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low at
rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
BW
1
- BW
4
write enable. On load write cycles (When R/W and ADV/LD are sampled low) the
appropriate byte write signal (BW - BW ) must be valid. The byte write signal
4
must also be valid on each cycle1of a burst write. Byte Write signals are ignored
when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later. BW
1
- BW can all be tied low if always doing write to the
4
entire 36-bit word.
Chip Enables
Synchronous active low chip enable. CE
1
and CE
2
are used with CE to
2
CE
1
, CE
2
enable the IDT71V547. (CE or CE sampled high or CE sampled low) and
1
ADV/LD low at the rising edge of c2lock, initiates a desele2ct cycle. This device has
a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect
is initiated.
CE2
CLK
Chip Enable
Clock
I
HIGH
N/A
Synchronout active high chip enable. CE is used with CE
1
and CE
2
to enable
the chip. CE
2
has inverted polarity but ot2herwise identical to CE
1
and CE
2
.
I
I/O
I
This is the clock input to the IDT71V547. Except for OE, all timing references for
the device are made with respect to the rising edge of CLK.
I/O - I/O
I/OP01 - I/O3P14
Data Input/Output
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the
rising edge of CLK. The data output path is flow-through (no output register).
Linear Burst
Order
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is
selected. When LBO is low the Linear burst sequence is selected. LBO is a static
DC input.
LBO
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V547.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can be
tied low.
OE
V
DD
SS
Power Supply
Ground
N/A
N/A
N/A
N/A
3.3V power supply input.
V
Ground pin.
3822 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
3
6.42
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