DATA SHEET
MOS FIELD EFFECT POWER TRANSISTORS
2SJ495
SWITCHING P-CHANNEL POWER MOS FET INDUSTRIAL USE
DESCRIPTION
PACKAGE DIMENSIONS
(in millimeter)
This product is P-Channel MOS Field Effect Transistor
designed for high current switching applications.
10.0 ± 0.3
4.5 ± 0.2
3.2 ± 0.2
2.7 ± 0.2
FEATURES
•
Super Low On-State Resistance
RDS(on)1 = 30 mΩ MAX. (VGS = –10 V, ID = –15 A)
RDS(on)2 = 56 mΩ MAX. (VGS = –4 V, ID = –15 A)
Low Ciss Ciss = 4120 pF TYP.
•
•
Built-in Gate Protection Diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage
VDSS
VGSS(AC)
VGSS(DC)
ID(DC)
ID(pulse)
PT
–60
m20
V
Gate to Source Voltage*
V
2.5 ± 0.1
0.65 ± 0.1
0.7 ± 0.1
2.54
1.3 ± 0.2
1.5 ± 0.2
2.54
Gate to Source Voltage
–20, 0
m30
V
Drain Current (DC)
A
Drain Current (pulse)**
m120
35
A
1. Gate
2. Drain
3. Source
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
W
W
°C
PT
2.0
1
2 3
Tch
150
Storage Temperature
Tstg
–55 to +150 °C
*f = 20 kHz, Duty Cycle ≤ 10% (+Side)
**PW ≤ 10 µs, Duty Cycle ≤ 1%
THERMAL RESISTANCE
Channel to Case
MP-45F (ISOLATED TO-220)
Rth(ch-c)
Rth(ch-A)
3.57
62.5
°C/W
°C/W
Drain
Channel to Ambient
Body
Diode
Gate
Gate Protection
Diode
Source
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this deveice
acutally used, an addtional protection circiut is externally required if a voltage exceeding the rated voltage may be applied
to this device.
Document No. D11267EJ2V0DS00 (2nd edition)
Date Published November 1997 N
Printed in Japan
1997
©