Datasheet > 晶体管 > 小信号场效应晶体管> 2N7002K-T1-GE3

2N7002K-T1-GE3

更新时间： 2024-02-16 10:38:42

品牌	Logo	应用领域
威世 - VISHAY		晶体小信号场效应晶体管开关光电二极管 PC
页数	文件大小	规格书
9页	219K
描述
N-Channel 60-V (D-S) MOSFET

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

2N7002K-T1-GE3 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOT-23
包装说明：	SMALL OUTLINE, R-PDSO-G3	针数：	3
Reach Compliance Code：	unknown	ECCN代码：	EAR99
风险等级：	0.49	Samacsys Confidence：	3
Samacsys Status：	Released	2D Presentation：	https://componentsearchengine.com/2D/0T/300555.1.1.png
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=300555	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=300555
3D View：	https://componentsearchengine.com/viewer/3D.php?partID=300555	Samacsys PartID：	300555
Samacsys Image：	https://componentsearchengine.com/Images/9/2N7002K-T1-GE3.jpg	Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/2N7002K-T1-GE3.jpg
Samacsys Pin Count：	3	Samacsys Part Category：	MOSFET (N-Channel)
Samacsys Package Category：	SOT23 (3-Pin)	Samacsys Footprint Name：	SOT-23 (TO-236) --
Samacsys Released Date：	2019-08-29 13:28:22	Is Samacsys：	N
其他特性：	LOW THRESHOLD, ESD PROTECTION, FAST SWITCHING	配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	60 V	最大漏极电流 (ID)：	0.3 A
最大漏源导通电阻：	4 Ω	FET 技术：	METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码：	TO-236AB	JESD-30 代码：	R-PDSO-G3
JESD-609代码：	e3	湿度敏感等级：	1
元件数量：	1	端子数量：	3
工作模式：	ENHANCEMENT MODE	最高工作温度：	150 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
极性/信道类型：	N-CHANNEL	功耗环境最大值：	0.35 W
最大功率耗散 (Abs)：	0.35 W	认证状态：	Not Qualified
表面贴装：	YES	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子位置：	DUAL
晶体管应用：	SWITCHING	晶体管元件材料：	SILICON
Base Number Matches：	1

2N7002K-T1-GE3 数据手册

AN807

Vishay Siliconix

Mounting LITTLE FOOT^RSOT-23 Power MOSFETs

Wharton McDaniel

Surface-mounted LITTLE FOOT power MOSFETs use integrated

circuit and small-signal packages which have been been modified

to provide the heat transfer capabilities required by power devices.

Leadframe materials and design, molding compounds, and die

attach materials have been changed, while the footprint of the

packages remains the same.

ambient air. This pattern uses all the available area underneath the

body for this purpose.

0.114

2.9

0.081

2.05

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix

MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET

footprint . In converting this footprint to the pad set for a power

device, designers must make two connections: an electrical

connection and a thermal connection, to draw heat away from the

package.

0.150

3.8

0.059

1.5

0.0394

1.0

0.037

0.95

FIGURE 1. Footprint With Copper Spreading

The electrical connections for the SOT-23 are very simple. Pin 1 is

the gate, pin 2 is the source, and pin 3 is the drain. As in the other

LITTLE FOOT packages, the drain pin serves the additional

function of providing the thermal connection from the package to

the PC board. The total cross section of a copper trace connected

to the drain may be adequate to carry the current required for the

application, but it may be inadequate thermally. Also, heat spreads

in a circular fashion from the heat source. In this case the drain pin

is the heat source when looking at heat spread on the PC board.

Since surface-mounted packages are small, and reflow soldering

is the most common way in which these are affixed to the PC

board, “thermal” connections from the planar copper to the pads

have not been used. Even if additional planar copper area is used,

there should be no problems in the soldering process. The actual

solder connections are defined by the solder mask openings. By

combining the basic footprint with the copper plane on the drain

pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23

package. This pattern shows the starting point for utilizing the

board area available for the heat spreading copper. To create this

pattern, a plane of copper overlies the drain pin and provides

planar copper to draw heat from the drain lead and start the

process of spreading the heat so it can be dissipated into the

A final item to keep in mind is the width of the power traces. The

absolute minimum power trace width must be determined by the

amount of current it has to carry. For thermal reasons, this

minimum width should be at least 0.020 inches. The use of wide

traces connected to the drain plane provides a low-impedance

path for heat to move away from the device.

Document Number: 70739

26-Nov-03

www.vishay.com

1...4 5 678 9

下载PDF

与2N7002K-T1-GE3相关器件

型号	品牌	描述	获取价格	数据表
2N7002KT1H	ONSEMI	320mA, 60V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-236, HALOGEN FREE AND ROHS COMPLIANT,	获取价格
2N7002KT3G	ONSEMI	Small Signal MOSFET 60 V, 380 mA, Single, Nâ	获取价格
2N7002KTB	PANJIT	60V N-Channel Enhancement Mode MOSFET - ESD Protected	获取价格
2N7002KTB_14	PANJIT	60V N-Channel Enhancement Mode MOSFET - ESD Protected	获取价格
2N7002KTB6	PANJIT	60V N-Channel Enhancement Mode MOSFET - ESD Protected	获取价格
2N7002K-TP	MCC	Small Signal Field-Effect Transistor, 0.34A I(D), 60V, 1-Element, N-Channel, Silicon, Meta	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

2N7002K-T1-GE3

2N7002K-T1-GE3 技术参数

2N7002K-T1-GE3 数据手册

与2N7002K-T1-GE3相关器件

与2N7002K-T1-GE3相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

2N7002K-T1-GE3

2N7002K-T1-GE3 技术参数

2N7002K-T1-GE3 数据手册

与2N7002K-T1-GE3相关器件

与2N7002K-T1-GE3相关文章

您还可以找

您在本页遇到什么问题？