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ZL50016_06 PDF预览

ZL50016_06

更新时间: 2024-10-28 04:23:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
81页 674K
描述
Enhanced 1 K Digital Switch

ZL50016_06 数据手册

 浏览型号ZL50016_06的Datasheet PDF文件第75页浏览型号ZL50016_06的Datasheet PDF文件第76页浏览型号ZL50016_06的Datasheet PDF文件第77页浏览型号ZL50016_06的Datasheet PDF文件第79页浏览型号ZL50016_06的Datasheet PDF文件第80页浏览型号ZL50016_06的Datasheet PDF文件第81页 
ZL50016  
Data Sheet  
AC Electrical Characteristics- Divided Clock Mode Output Timing  
Characteristic  
Sym.  
Min.  
Max.  
Units  
1
2
3
CKo0 to CKo1 (8.192 MHz) delay  
tC1D  
tC2D  
tC3D  
-1  
-1  
-2  
2
3
2
ns  
ns  
ns  
CKo0 to CKo2 (16.384 MHz) delay  
CKo0 to CKo3 (16.384 MHz/8.192 MHz/4.096 MHz) delay  
† Characteristics are over recommended operating conditions unless otherwise stated.  
AC Electrical Characteristics- Multiplied Clock Mode Output Timing  
Characteristic  
Sym.  
Min.  
Max.  
Units  
1
2
3
CKo0 to CKo1 (8.192 MHz) delay  
CKo0 to CKo2 (16.384 MHz) delay  
tC1D  
tC2D  
tC3D  
-1  
-1  
-1  
2
3
3
ns  
ns  
ns  
CKo0 to CKo3  
(32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay  
† Characteristics are over recommended operating conditions unless otherwise stated.  
t
FPD  
FPo0  
V
CT  
V
CKo0  
CT  
(4.096 MHz)  
t
t
C1D  
V
CKo1  
CT  
(8.192 MHz)  
C2D  
V
CKo2  
CT  
CT  
(16.384 MHz)  
t
C3D  
V
CKo3  
(32.768 MHz)  
Figure 40 - Output Timing (ST-BUS Format)  
78  
Zarlink Semiconductor Inc.  

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