Datasheet > ZL50018GAG2

ZL50018GAG2

更新时间： 2024-01-01 20:09:59

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信集成电路
页数	文件大小	规格书
136页	1406K
描述
2 K Digital Switch with Enhanced Stratum 3 DPLL

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ZL50018GAG2 技术参数

生命周期：	Transferred	包装说明：	BGA,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.63	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e1	长度：	17 mm
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
认证状态：	Not Qualified	座面最大高度：	1.8 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	17 mm	Base Number Matches：	1

ZL50018GAG2 数据手册

ZL50018

2 K Digital Switch with Enhanced

Stratum 3 DPLL

Data Sheet

November 2006

Features

•

2048 channel x 2048 channel non-blocking digital

Ordering Information

Time Division Multiplex (TDM) switch at 8.192

and 16.384 Mbps or using a combination of ports

running at 2.048, 4.096, 8.192 and/or

16.384 Mbps

ZL50018GAC

ZL50018QCC

ZL50018QCG1

256 Ball PBGA

256 Lead LQFP

256 Lead LQFP*

Trays

Trays, Bake &

Drypack

ZL50018GAG2

256 Ball PBGA**

Trays, Bake &

•

32 serial TDM input, 32 serial TDM output

Drypack

streams

*Pb Free Matte Tin

**Pb Free Tin/Silver/Copper

Integrated Digital Phase-Locked Loop (DPLL)

exceeds Telcordia GR-1244-CORE Stratum 3

specifications

-40°C to +85°C

•

Output clocks have less than 1 ns of jitter (except

hysteresis range, phase slope, lock detector

range)

for the 1.544 MHz output)

DPLL provides holdover, freerun and jitter

attenuation features with four independent

reference source inputs

•

Exceptional input clock cycle to cycle variation

tolerance (20 ns for all rates)

Output streams can be configured as bi-

directional for connection to backplanes

•

Programmable key DPLL parameters (filter

corner frequency, locking range, auto-holdover

V_{DD_COREA}

V_{DD_IOA}

RESET

V_{DD_CORE}

V_{DD_IO}

V_SS

ODE

P/S Converter

STio[31:0]

S/P Converter

Input Timing

Data Memory

STi[31:0]

FPi

CKi

Output HiZ

Control

STOHZ[15:0]

MODE_4M0

MODE_4M1

Connection Memory

REF0

REF1

REF2

REF3

FPo[3:0]

CKo[5:0]

FPo_OFF[2:0]

Output Timing

Test Port

DPLL

OSC

REF_FAIL0

REF_FAIL1

REF_FAIL2

REF_FAIL3

Internal Registers &

Microprocessor Interface

OSC_EN

Figure 1 - ZL50018 Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...136

下载PDF

与ZL50018GAG2相关器件

型号	品牌	描述	获取价格	数据表
ZL50018QCC	ZARLINK	2 K Digital Switch with Enhanced Stratum 3 DPLL	获取价格
ZL50018QCG1	ZARLINK	2 K Digital Switch with Enhanced Stratum 3 DPLL	获取价格
ZL50019	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50019_06	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50019GAC	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50019GAG2	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格