ZL50019
Enhanced 2 K Digital Switch with
Stratum 4E DPLL
Data Sheet
November 2006
Features
•
2048 channel x 2048 channel non-blocking digital
Ordering Information
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and 16.384 Mbps
ZL50019GAC
ZL50019QCC
256 Ball PBGA
Trays
Trays
256 Lead LQFP
ZL50019QCG1 256 Lead LQFP* Trays, Bake &
Drypack
•
•
32 serial TDM input, 32 serial TDM output
ZL50019GAG2
256 Ball PBGA** Trays, Bake &
Drypack
streams
*Pb Free Matte Tin
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 4E
specifications
**Pb Free Tin/Silver/Copper
-40°C to +85°C
•
•
Output clocks have less than 1 ns of jitter (except
•
Per-stream input and output data rate conversion
selection at 2.048, 4.096, 8.192 or 16.384 Mbps.
Input and output data rates can differ
for the 1.544 MHz output)
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
•
•
•
Per-stream high impedance control outputs
(STOHZ) for 16 output streams
•
•
Exceptional input clock cycle to cycle variation
Per-stream input bit delay with flexible sampling
point selection
tolerance (20 ns for all rates)
Output streams can be configured as bi-
directional for connection to backplanes
Per-stream output bit and fractional bit
advancement
VDD_COREA
VDD_IOA
RESET
VDD_CORE
VDD_IO
VSS
ODE
P/S Converter
STio[31:0]
S/P Converter
Input Timing
Data Memory
STi[31:0]
FPi
CKi
Output HiZ
Control
STOHZ[15:0]
MODE_4M0
MODE_4M1
Connection Memory
REF0
REF1
REF2
REF3
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
Output Timing
Test Port
DPLL
OSC
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
Internal Registers &
Microprocessor Interface
OSC_EN
Figure 1 - ZL50019 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.