ZL50016
Data Sheet
tFPW23
VCT
FPo2/3
CKo2/3
tFODF23
tFODR23
tCKP23
tCKH23
tCKL23
VCT
trCK23
tfCK23
Output Frame Boundary
Figure 38 - FPo2 and CKo2 Timing Diagram
AC Electrical Characteristics† - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Divided Clock Mode and Multiplied Clock
Mode with Less than 10 ns of Input Cycle to Cycle Variation
Characteristic
FPo2 Output Pulse Width
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW23
tFODF23
56
25
61
66
36
ns
ns
CL = 30 pF
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR23
25
36
ns
4
5
6
7
CKo2 Output Clock Period
CKo2 Output High Time
CKo2 Output Low Time
CKo2 Output Rise/Fall Time
tCKP23
tCKH23
tCKL23
56
25
25
61
66
36
36
5
ns
ns
ns
ns
CL = 30 pF
t
rCK23, tfCK23
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
AC Electrical Characteristics† - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Multiplied Clock Mode with More than
10 ns of Input Cycle to Cycle Variation
Characteristic
FPo2 Output Pulse Width
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW23
tFODF23
56
25
61
66
36
ns
ns
CL = 30 pF
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR23
25
36
ns
4
5
6
7
CKo2 Output Clock Period
CKo2 Output High Time
CKo2 Output Low Time
CKo2Output Rise/Fall Time
tCKP2
tCKH23
tCKL23
47
17
17
61
76
43
43
5
ns
ns
ns
ns
CL = 30 pF
t
rCK23, tfCK23
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
76
Zarlink Semiconductor Inc.