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ZL50016_06 PDF预览

ZL50016_06

更新时间: 2024-10-28 04:23:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
81页 674K
描述
Enhanced 1 K Digital Switch

ZL50016_06 数据手册

 浏览型号ZL50016_06的Datasheet PDF文件第74页浏览型号ZL50016_06的Datasheet PDF文件第75页浏览型号ZL50016_06的Datasheet PDF文件第76页浏览型号ZL50016_06的Datasheet PDF文件第78页浏览型号ZL50016_06的Datasheet PDF文件第79页浏览型号ZL50016_06的Datasheet PDF文件第80页 
ZL50016  
Data Sheet  
tFPW3  
VCT  
FPo3  
CKo3  
tFODF3  
tFODR3  
tCKP3  
tCKH3  
tCKL3  
VCT  
trCK3  
tfCK3  
Output Frame Boundary  
Figure 39 - FPo3 and CKo3 Timing Diagram  
AC Electrical Characteristics- FPo3/CKo3 (32.768 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less  
than 10 ns of Input Cycle to Cycle Variation  
Characteristic  
FPo3 Output Pulse Width  
FPo3 Output Delay from the FPo3 falling edge  
to the output frame boundary  
Sym.  
Min. Typ.Max. Units  
Notes  
1
2
tFPW3  
tFODF3  
27  
10  
30.5  
34  
18  
ns  
ns  
CL = 30 pF  
3
FPo3 Output Delay from the output frame  
boundary to the FPo3 rising edge  
tFODR3  
12  
21  
ns  
4
5
6
7
CKo3 Output Clock Period  
CKo3 Output High Time  
CKo3 Output Low Time  
CKo3 Output Rise/Fall Time  
tCKP3  
tCKH3  
tCKL3  
27  
12  
12  
30.5  
34  
19  
19  
5
ns  
ns  
ns  
ns  
CL = 30 pF  
t
rCK3, tfCK3  
† Characteristics are over recommended operating conditions unless otherwise stated.  
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-  
tion testing.  
AC Electrical Characteristics- FPo3/CKo3 (32.768 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Input Cycle  
to Cycle Variation  
Characteristic  
FPo3 Output Pulse Width  
FPo3 Output Delay from the FPo3 falling edge  
to the output frame boundary  
Sym.  
Min. Typ.Max. Units  
Notes  
1
2
tFPW3  
tFODF3  
27  
12  
30.5  
34  
19  
ns  
ns  
CL = 30 pF  
3
FPo3 Output Delay from the output frame  
boundary to the FPo3 rising edge  
tFODR3  
12  
19  
ns  
4
5
6
7
CKo3 Output Clock Period  
CKo3 Output High Time  
CKo3 Output Low Time  
CKo3 Output Rise/Fall Time  
tCKP3  
tCKH3  
tCKL3  
17  
5
12  
30.5  
44  
29  
18  
5
ns  
ns  
ns  
ns  
CL = 30 pF  
trCK3, tfCK3  
† Characteristics are over recommended operating conditions unless otherwise stated.  
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-  
tion testing.  
77  
Zarlink Semiconductor Inc.  

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