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XQR18V04CCG44M

更新时间： 2024-09-17 15:58:31
品牌 Logo 应用领域
赛灵思 - XILINX 内存集成电路
页数 文件大小 规格书
15页 754K
描述
Configuration Memory, 512X8, Parallel/serial, CMOS, CQCC44, CERAMIC, LCC-44

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中文翻译

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XQR18V04CCG44M 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：LCC包装说明：QCCJ,
针数：44Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.83Is Samacsys：N
JESD-30 代码：S-CQCC-J44长度：16.51 mm
内存密度：4096 bit内存集成电路类型：CONFIGURATION MEMORY
内存宽度：8功能数量：1
端子数量：44字数：512 words
字数代码：512工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：512X8封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL/SERIAL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：4.826 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：40k Rad(Si) V
宽度：16.51 mmBase Number Matches：1

XQR18V04CCG44M 数据手册

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ARCHIVED DATA SHEET - NO LONGER SUPPORTED  
<
B
L
R
QPro XQR18V04 Radiation-Tolerant  
4-Mbit QML ISP Configuration Flash PROM  
DS082 (v1.6) March 15, 2007  
Product Specification  
Features  
•
•
•
•
•
•
•
Operating temperature range: –55°C to +100°C  
Program/erase temperature range: 0°C to +85°C  
JTAG operating temperature range: 0°C to +85°C  
•
•
•
IEEE STD 1149.1 Boundary-Scan (JTAG) support  
Cascadable for storing longer or multiple bitstreams  
Dual configuration modes  
2
Latch-up immune to LET >120 MeV/cm /mg  
♦
♦
Serial Slow/Fast configuration (up to 20 MHz)  
Parallel (up to 160 Mbps at 20 MHz)  
Guaranteed TID of 30 kRad(Si) per spec 1019.5  
Fabricated on epitaxial substrate  
•
•
•
•
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals  
3.3V or 2.5V output capability  
Low-power advanced CMOS FLASH process memory  
cells immune to static single event upset  
Available in CC44 package  
•
•
Supports SEU scrubbing for Virtex™ series FPGAs  
Design support using the Xilinx Alliance Series™ and  
Xilinx Foundation Series™ software packages  
In-system programmable 3.3V PROMs for  
configuration of Xilinx FPGAs  
•
JTAG command initiation of standard FPGA  
configuration  
♦
♦
Endurance of 2,000 program/erase cycles  
Program/erase over operational temperature range  
Description  
The QPro™ XQR18V04 is a 3.3V latch-up-immune,  
static-SEU-immune, rewritable radiation-tolerant QML 4-Mbit  
in-system-programmable configuration flash PROM,  
providing a reliable non-volatile method for storing large Xilinx  
FPGA configuration bitstreams used in space flight systems.  
When the FPGA is in Slave SelectMAP or Express mode,  
an external oscillator generates the configuration clock that  
drives the PROM and the FPGA. A free-running, external  
oscillator can be used. After CE and OE are enabled, data is  
available on the PROM’s DATA (D0-D7) pins. New data is  
available a short access time after each rising clock edge.  
The data is clocked into the FPGA on the following rising  
edge of the CCLK. See Figure 3, page 4.  
When the FPGA is in Master Serial mode, it generates a  
configuration clock that drives the PROM. A short access  
time after CE and OE are enabled, data is available on the  
PROM DATA (D0) pin that is connected to the FPGA D  
Multiple devices can be cascaded by using the CEO output  
to drive the CE input of the following device. The clock  
inputs and the DATA outputs of all PROMs in this chain are  
interconnected. The XQR18V04 is compatible and can be  
cascaded with other configuration PROMs such as the  
XQR1701L and XQR17V16 one-time programmable  
configuration PROMs.  
IN  
pin. New data is available a short access time after each  
rising clock edge. The FPGA generates the appropriate  
number of clock pulses to complete the configuration. When  
the FPGA is in Slave Serial mode, the PROM and the FPGA  
are clocked by an external clock.  
When the FPGA is in Master SelectMAP mode, the FPGA  
generates a configuration clock that drives the PROM.  
©2001–2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS082 (v1.6) March 15, 2007  
www.xilinx.com  
Product Specification  
1
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与XQR18V04CCG44M相关器件

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XQR18V04VQ44N XILINX

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XQR2V1000-4BG575N XILINX

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 		Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA575
XQR2V1000-4BG575R XILINX

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 		Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA575
XQR2V1000-4FG456N XILINX

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 		Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA456
XQR2V1000-4FGG456N XILINX

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 		Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, CMOS, PBGA456, 1 MM PITCH
XQR2V1000-4FGG456R XILINX

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 		Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, CMOS, PBGA456, 1 MM PITCH
XQR2V3000-4BG728R XILINX

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 		Field Programmable Gate Array, 3584 CLBs, 3000000 Gates, 650MHz, 32256-Cell, CMOS, PBGA728
XQR2V3000-4BGG728N XILINX

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 		Field Programmable Gate Array, 3584 CLBs, 3000000 Gates, 650MHz, CMOS, PBGA728, 1.27 MM PI
XQR2V3000-4BGG728R XILINX

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 		Field Programmable Gate Array, 3584 CLBs, 3000000 Gates, 650MHz, CMOS, PBGA728, 1.27 MM PI

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