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XQR2V1000-4BG575R PDF预览

XQR2V1000-4BG575R

更新时间： 2024-09-17 20:01:35
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
123页 1393K
描述
Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 650MHz, 11520-Cell, CMOS, PBGA575, 1.27 MM PITCH, PLASTIC, MS-034BAN-1, BGA-575

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XQR2V1000-4BG575R 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA575,24X24,50
针数：575Reach Compliance Code：not_compliant
ECCN代码：USML XV(E)HTS代码：8542.39.00.01
风险等级：5.87最大时钟频率：650 MHz
CLB-Max的组合延迟：0.44 nsJESD-30 代码：S-PBGA-B575
JESD-609代码：e0长度：31 mm
湿度敏感等级：3可配置逻辑块数量：1280
等效关口数量：1000000输入次数：328
逻辑单元数量：11520输出次数：328
端子数量：575最高工作温度：125 °C
最低工作温度：-55 °C组织：1280 CLBS, 1000000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA575,24X24,50封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：1.5,1.5/3.3,3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.6 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：31 mmBase Number Matches：1

XQR2V1000-4BG575R 数据手册

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QPro Virtex-II 1.5V Radiation-Hardened  
QML Platform FPGAs  
DS124 (v1.2) December 4, 2006  
Product Specification  
Summary of Radiation Hardened QPro™ Virtex-II Features  
•
Industry First Radiation Hardened Platform FPGA  
•
High-Performance Clock Management Circuitry  
Solution  
♦
Up to 12 DCM (Digital Clock Manager) modules  
•
•
•
Guaranteed total ionizing dose to 200K Rad(Si)  
-
-
-
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
2
Latch-up immune to LET > 160 MeV-cm /mg  
SEU in GEO upsets < 1.5E-6 per device day achievable  
with recommended redundancy implementation  
♦
16 global clock multiplexer buffers  
•
•
•
•
•
Certified to MIL-PRF-38535 (Qualified Manufacturer  
Listing)  
•
•
Active Interconnect Technology  
♦
♦
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of fanout  
Guaranteed over the full military temperature range  
(–55°C to +125°C)  
0.15 µm 8-Layer Metal Process with 0.12 µm  
High-Speed Transistors  
SelectIO™-Ultra Technology  
♦
♦
♦
Up to 824 user I/Os  
Ceramic and Plastic Wire-Bond and Flip-Chip Grid  
Array Packages  
19 single-ended and six differential standards  
Programmable sink current (2 mA to 24 mA) per  
I/O  
IP-Immersion Architecture  
♦
♦
♦
Densities from 1M to 6M system gates  
300+ MHz internal clock speed (Advance Data)  
622+ Mb/s I/O (Advance Data)  
♦
♦
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
Differential Signaling  
•
•
SelectRAM™ Memory Hierarchy  
-
622 Mb/s Low-Voltage Differential Signaling  
I/O (LVDS) with current mode drivers  
Bus LVDS I/O  
♦
2.5 Mb of dual-port RAM in 18 Kbit block  
SelectRAM resources  
-
-
♦
Up to 1 Mb of distributed SelectRAM resources  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
High-Performance Interfaces to External Memory  
-
-
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
♦
DRAM interfaces  
-
-
-
SDR/DDR SDRAM  
Network FCRAM  
Reduced Latency DRAM  
Built-in DDR input and output registers  
♦
Proprietary high-performance SelectLink Technology  
-
-
-
High-bandwidth data path  
♦
♦
SRAM interfaces  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
-
-
SDR/DDR SRAM  
QDR SRAM  
•
•
Supported by Xilinx Foundation Series™ and Alliance  
Series™ Development Systems  
CAM interfaces  
•
•
Arithmetic Functions  
♦
♦
♦
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
♦
♦
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
Flexible Logic Resources  
SRAM-Based In-System Configuration  
♦
Up to 67,584 internal registers/latches with Clock  
Enable  
♦
♦
♦
♦
♦
Fast SelectMAP configuration  
IEEE 1532 support  
♦
Up to 67,584 look-up tables (LUTs) or cascadable  
16-bit shift registers  
Partial reconfiguration  
Unlimited reprogrammability  
Readback capability  
♦
♦
Wide multiplexers and wide-input function support  
Horizontal cascade chain and sum-of-products  
support  
•
•
1.5V (V  
CCAUX  
) Core Power Supply, Dedicated 3.3V  
CCINT  
V
Auxiliary and V  
I/O Power Supplies  
♦
Internal 3-state busing  
CCO  
IEEE 1149.1 Compatible Boundary-Scan Logic Support  
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS124 (v1.2) December 4, 2006  
www.xilinx.com  
Product Specification  
1
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