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XQR4000XL

更新时间: 2024-11-06 23:34:03
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其他 - ETC /
页数 文件大小 规格书
20页 197K
描述
QPRO XQR4000XL Radiation Hardened FPGAs

XQR4000XL 数据手册

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0
R
QPRO XQR4000XL Radiation  
Hardened FPGAs  
0
2
DS071 (v1.1) June 25, 2000  
Product Specification  
Systems-oriented features  
XQR4000XL Series Features  
-
IEEE 1149.1-compatible boundary scan logic  
support  
Radiation-hardened FPGAs for space and satellite  
applications  
-
-
-
Individually programmable output slew rate  
Programmable input pull-up or pull-down resistors  
12 mA sink current per output  
Guaranteed total ionizing dose  
Latch-up immune  
Low soft upset rate  
Configured by loading binary file  
Unlimited reprogrammability  
Readback capability  
Guaranteed to meet full electrical specifications over  
–55°C to +125°C  
-
Available in -3 speed  
-
-
Program verification  
Internal node observability  
System featured FPGAs  
-
SelectRAM™ memory: on-chip ultra-fast RAM with  
Development system runs on most common computer  
platforms  
·
synchronous write option  
·
dual-port RAM option  
-
-
-
Interfaces to popular design environments  
Fully automatic mapping, placement and routing  
Interactive design editor for design optimization  
-
-
-
-
-
-
-
Abundant flip-flops  
Flexible function generators  
Dedicated high-speed carry logic  
Wide edge decoders on each edge  
Hierarchy of interconnect lines  
Internal 3-state bus capability  
Eight global low-skew clock or signal distribution  
networks  
Highest capacity: over 130,000 usable gates  
Buffered interconnect for maximum speed  
New latch capability in configurable logic blocks  
Improved VersaRingI/O interconnect for better fixed  
pinout flexibility  
-
Virtually unlimited number of clock signals  
System performance beyond 60 MHz  
Flexible array architecture  
Optional multiplexer or 2-input function generator on  
device outputs  
Low power segmented routing architecture  
5V tolerant I/Os  
Advanced 0.35µ process  
Processed on Xilinx QML line  
Table 1: XQR4000XL Series Radiation Hardened Field Programmable Gate Arrays  
Max.  
Logic  
Gates  
Typical  
Max. RAM  
Bits  
Gate Range  
(Logic and  
Number  
of  
Matrix CLBs Flip-Flops  
Max.  
User  
I/O  
Logic  
CLB  
Total  
(1)  
Device  
Cells (No RAM) (No Logic)  
RAM)  
Packages  
CB228  
XQR4013XL 1,368  
XQR4036XL 3,078  
XQR4062XL 5,472  
Notes:  
13,000  
36,000  
62,000  
18,432  
41,472  
73,728  
10,000 - 30,000 24 x 24  
576  
1,536  
3,168  
5,376  
192  
288  
384  
22,000 - 65,000 36 x 36 1,296  
40,000 - 130,000 48 x 48 2,304  
CB228  
CB228  
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.  
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS071 (v1.1) June 25, 2000  
Product Specification  
www.xilinx.com  
1-800-255-7778  
1
This Material Copyrighted by Its Respective Manufacturer  

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