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XQR4VSX55-10CF1140V PDF预览

XQR4VSX55-10CF1140V

更新时间： 2024-02-23 01:12:30
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
36页 287K
描述
Field Programmable Gate Array, 6144 CLBs, 1028MHz, 55296-Cell, CMOS, CBGA1140, CERAMIC, CGA-1140

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XQR4VSX55-10CF1140V 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：CGA包装说明：CGA, PGA1140,34X34,39
针数：1140Reach Compliance Code：unknown
ECCN代码：9A515.E.2HTS代码：8542.39.00.01
风险等级：5.86最大时钟频率：1028 MHz
JESD-30 代码：S-CBGA-X1140长度：35 mm
可配置逻辑块数量：6144输入次数：640
逻辑单元数量：55296输出次数：640
端子数量：1140最高工作温度：125 °C
最低工作温度：-55 °C组织：6144 CLBS
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：CGA
封装等效代码：PGA1140,34X34,39封装形状：SQUARE
封装形式：GRID ARRAY电源：1.2,2.5,3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
筛选级别：38535V;38534K;883S座面最大高度：8.47 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.26 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：UNSPECIFIED
端子节距：1 mm端子位置：BOTTOM
宽度：35 mmBase Number Matches：1

XQR4VSX55-10CF1140V 数据手册

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R
Space-Grade Virtex-4QV FPGAs:  
DC and Switching Characteristics  
DS680 (v2.0) April 12, 2010  
Product Specification  
Virtex-4QV FPGA Electrical Characteristics  
Space-grade, radiation-tolerant Virtex®-4QV FPGAs are  
available in the -10 speed grade and qualified for military  
parameters included are common to popular designs and  
typical applications.  
(T = –55° C to +125°C) operational temperatures.  
j
This Virtex-4QV FPGA data sheet is part of an overall set of  
documentation on the Virtex-4 family of FPGAs available on  
the Xilinx website:  
Virtex-4QV FPGA DC and AC characteristics are specified  
for military temperatures only. Except the operating  
temperature range or unless otherwise noted, all the DC  
and AC electrical parameters are the same for a particular  
speed grade (that is, the timing characteristics of a  
-10 speed grade military device are the same as for a  
-10 speed grade industrial device).  
•
DS653, Space-Grade Virtex-4QV Family Overview  
UG070, Virtex-4 FPGA User Guide  
•
•
•
•
UG071, Virtex-4 FPGA Configuration Guide  
UG073, XtremeDSP for Virtex-4 FPGAs  
All supply voltage and junction temperature specifications  
are representative of worst-case conditions. The  
UG496, Virtex-4QV FPGA Ceramic Packaging and  
Pinout Specifications  
•
UG072, Virtex-4 FPGA PCB Designer’s Guide  
Virtex-4QV FPGA DC Characteristics  
Table 1: Absolute Maximum Ratings  
Symbol  
VCCINT  
Description  
Internal supply voltage relative to GND  
Units  
–0.5 to 1.32  
–0.5 to 3.0  
V
V
VCCAUX  
VCCO  
VBATT  
VREF  
Auxiliary supply voltage relative to GND  
Output drivers supply voltage relative to GND  
Key memory battery backup supply  
Input reference voltage  
–0.5 to 3.75  
–0.5 to 4.05  
–0.3 to 3.75  
–0.75 to 4.05  
–0.85 to 4.3  
–0.75 to VCCO +0.5  
–0.75 to 4.05  
–0.85 to 4.3  
–0.75 to VCCO +0.5  
–65 to 150  
V
V
V
I/O input voltage relative to GND (all user and dedicated I/Os)  
I/O input voltage relative to GND(3) (restricted to maximum of 100 user I/Os)(4)  
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)  
Voltage applied to 3-state 3.3V output(3) (all user and dedicated I/Os)  
Voltage applied to 3-state 3.3V output(3) (restricted to maximum of 100 user I/Os)(4)  
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)  
Storage temperature (ambient)  
V
VIN  
V
V
V
VTS  
V
V
TSTG  
TSOL  
TJ  
° C  
° C  
° C  
Maximum soldering temperature(2)  
Maximum junction temperature(2)  
+220  
+125  
Notes:  
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,  
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.  
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.  
2. For soldering guidelines and thermal considerations, see the Virtex-4QV FPGA Ceramic Packaging and Pinout Specifications on the Xilinx  
website.  
3. For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines, Table 6-38.  
4. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data  
period. There are no bank restrictions.  
© Copyright 2008–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.  
DS680 (v2.0) April 12, 2010  
www.xilinx.com  
Product Specification  
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