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XQR5VFX130-1CN1752B PDF预览

XQR5VFX130-1CN1752B

更新时间： 2024-09-17 18:32:31
品牌 Logo 应用领域
赛灵思 - XILINX 栅可编程逻辑
页数 文件大小 规格书
16页 470K
描述
Field Programmable Gate Array, 10240 CLBs, CMOS, CBGA1752, CGA-1752

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XQR5VFX130-1CN1752B 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：CGA-1752Reach Compliance Code：compliant
ECCN代码：9A515.E.2HTS代码：8542.39.00.01
风险等级：5.81JESD-30 代码：S-CBGA-X1752
长度：45 mm可配置逻辑块数量：10240
端子数量：1752最高工作温度：125 °C
最低工作温度：-55 °C组织：10240 CLBS
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：CGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：8.8 mm
最大供电电压：1.05 V最小供电电压：0.95 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：UNSPECIFIED端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：1M Rad(Si) V宽度：45 mm
Base Number Matches：1

XQR5VFX130-1CN1752B 数据手册

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Radiation-Hardened, Space-Grade  
Virtex-5QV Family Overview  
0
0
DS192 (v1.4) November 12, 2014  
Product Specification  
General Description  
The only reprogrammable and highest density radiation-hardened (RH) FPGA, the space-grade Virtex®-5QV FPGA provides RH  
by design technology to meet the requirements of space applications that demand high-performance as well as high reliability. For  
years, ASICs were the only solution available to system designers of high-performance space applications with long development  
and fabrication times as well as high non-recurring engineering (NRE) costs. The Virtex-5QV FPGA combines unparalleled  
density, performance, and radiation hardening with the flexibility of reconfigurability without the high risk of ASICs.  
The Virtex-5QV device provides the compelling set of performance, features, and solutions for the radiation-hardened systems  
market. Using the second generation Advanced Silicon Modular Block (ASMBL™) column-based architecture, the Virtex-5QV  
FPGA contains an array of features to address the needs of a wide variety of advanced logic designs and many dedicated  
system-level blocks, including powerful 36 Kb block RAM and FIFOs, second-generation 25 x 18 DSP slices, SelectIO™  
technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, enhanced clock  
management tiles with integrated digital clock managers (DCMs), phase-locked-loop (PLL) clock generators, and advanced  
configuration options. Additional features include power-optimized, high-speed serial transceiver blocks for enhanced serial  
connectivity, PCI Express® compliant integrated Endpoint blocks, and tri-mode Ethernet Media Access Controllers (MACs). These  
features allow advanced logic designers to build the highest levels of connectivity and performance into their FPGA-based systems.  
Built on a proven 65-nm copper process technology, the Virtex-5QV FPGA is a modern programmable alternative to custom ASIC  
technology. The Virtex-5QV FPGA offers the latest solution for addressing the needs of critical space missions where design changes  
can be accommodated late in the program or through reprogrammability, even after launch.  
A Virtex-5QV FPGA provides exceptional hardness to single-event upsets (SEUs), total immunity to single-event latch-ups (SELs),  
total ionizing doses (TIDs) of over 1 Mrad(Si), and datapath protection from single-event transients (SETs). Compatibility with the  
commercial and defense-grade Virtex-5 FPGAs allows for low-cost, rapid prototyping and easy design migration to flight hardware  
without the need for PCB changes.  
Table 1: Virtex-5QV FPGA Family Members  
Endpoint  
Blocks  
for  
Max  
RocketIO  
GTX  
Configurable Logic Blocks (CLBs)  
Block RAM Blocks  
Total  
I/O  
Max  
User  
I/O(8)  
DSP48E  
Slices(2)  
CMTs  
Ethernet  
MACs(5)  
Array  
CLB  
Max  
Device  
(4)  
Logic  
Cells  
18 Kb  
Max  
(Kb)  
Banks  
(Row x Slices Distributed  
36 Kb  
PCI  
Transceivers  
(3)  
(7)  
(1)  
(6)  
Col)  
RAM (Kb)  
Express  
XQR5VFX130 131,072 200 x 56 20,480  
1,580  
320  
596  
298 10,728  
6
3
6
18  
24  
836  
Notes:  
1. Virtex-5QV FPGA CLB slices are organized differently from previous generations. Each CLB slice contains four LUTs and four flip-flops (previously it  
was two LUTs and two flip-flops.)  
2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.  
3. Block RAMs are fundamentally 36 Kb in size. Each block can also be used as two independent 18 Kb blocks.  
4. Each CMT contains two DCMs and one PLL.  
5. This table lists separate Ethernet MACs per device.  
6. RocketIO™ GTX transceivers are designed to run from 150 Mb/s to 4.25 Gb/s.  
7. Includes configuration Bank 0.  
8. This number does not include RocketIO transceivers.  
© Copyright 2010–2014 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are  
trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.  
DS192 (v1.4) November 12, 2014  
www.xilinx.com  
Product Specification  
1
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