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XQR2V3000-4BGG728R PDF预览

XQR2V3000-4BGG728R

更新时间： 2024-11-07 20:41:27
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
128页 2777K
描述
Field Programmable Gate Array, 3584 CLBs, 3000000 Gates, 650MHz, CMOS, PBGA728, 1.27 MM PITCH, PLASTIC, MS-034-BAR-1, BGA-728

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XQR2V3000-4BGG728R 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：728
Reach Compliance Code：compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.82
最大时钟频率：650 MHzCLB-Max的组合延迟：0.44 ns
JESD-30 代码：S-PBGA-B728JESD-609代码：e1
长度：35 mm湿度敏感等级：3
可配置逻辑块数量：3584等效关口数量：3000000
端子数量：728最高工作温度：125 °C
最低工作温度：-55 °C组织：3584 CLBS, 3000000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：245可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.6 mm
最大供电电压：1.575 V最小供电电压：1.425 V
标称供电电压：1.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：35 mm
Base Number Matches：1

XQR2V3000-4BGG728R 数据手册

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0
R
QPro Virtex-II 1.5V Radiation  
Hardened QML Platform FPGAs  
0
0
DS124 (v1.1) January 8, 2004  
Product Specification  
Summary of Radiation Hardened QPro™ Virtex™-II Features  
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
•
Industry First Radiation Hardened Platform FPGA  
Solution  
•
•
•
Guaranteed total ionizing dose to 200K Rad(si)  
-
16 global clock multiplexer buffers  
2
Latch-up immune to LET > 160 MeV-cm /mg  
•
•
Active Interconnect Technology  
SEU in GEO upsets < 1.5E-6 per device day  
achievable with recommended redundancy  
implementation  
Certified to MIL-PRF-38535 (Qualified Manufacturer  
Listing)  
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
•
•
•
•
SelectIO™-Ultra Technology  
-
-
-
Up to 824 user I/Os  
Guaranteed over the full military temperature range  
(–55°C to +125° C)  
Ceramic and Plastic Wire-Bond and Flip-Chip Grid  
Array Packages  
IP-Immersion Architecture  
19 single-ended and six differential standards  
Programmable sink current (2 mA to 24 mA) per  
I/O  
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
Differential Signaling  
-
-
-
-
-
Densities from 1M to 6M system gates  
300+ MHz internal clock speed (Advance Data)  
622+ Mb/s I/O (Advance Data)  
·
622 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
Built-in DDR input and output registers  
·
·
•
•
SelectRAM™ Memory Hierarchy  
-
2.5 Mb of dual-port RAM in 18 Kbit block  
SelectRAM resources  
·
·
-
Up to 1 Mb of distributed SelectRAM resources  
High-Performance Interfaces to External Memory  
-
DRAM interfaces  
-
Proprietary high-performance SelectLink  
Technology  
·
·
·
·
·
·
SDR/DDR SDRAM  
Network FCRAM  
Reduced Latency DRAM  
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
-
-
SRAM interfaces  
·
SDR/DDR SRAM  
•
•
Supported by Xilinx Foundation Series™ and Alliance  
Series™ Development Systems  
·
QDR SRAM  
CAM interfaces  
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
•
•
Arithmetic Functions  
-
-
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
SRAM-Based In-System Configuration  
Flexible Logic Resources  
-
-
-
-
-
Fast SelectMAP configuration  
IEEE 1532 support  
Partial reconfiguration  
Unlimited reprogrammability  
Readback capability  
-
Up to 67,584 internal registers/latches with Clock  
Enable  
-
Up to 67,584 look-up tables (LUTs) or cascadable  
16-bit shift registers  
-
-
Wide multiplexers and wide-input function support  
Horizontal cascade chain and sum-of-products  
support  
•
•
0.15 µm 8-Layer Metal Process with 0.12 µm  
High-Speed Transistors  
1.5V (VCCINT) Core Power Supply, Dedicated 3.3V  
VCCAUX Auxiliary and VCCO I/O Power Supplies  
-
Internal 3-state busing  
•
High-Performance Clock Management Circuitry  
Up to 12 DCM (Digital Clock Manager) modules  
•
IEEE 1149.1 Compatible Boundary-Scan Logic Support  
-
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS124 (v1.1) January 8, 2004  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  
1234567...128

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