WCMA2016U4B
Switching Characteristics Over the Operating Range[8]
55ns
70 ns
Parameter
READ CYCLE
Description
Min
55
Max
Min
70
Max
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[9]
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
10
10
55
25
70
35
5
10
0
5
10
0
[9, 11]
OE HIGH to High Z
25
25
25
25
[9]
CE LOW to Low Z
CE HIGH to High Z[9, 11]
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z[9]
55
55
70
70
tDBE
[10]
tLZBE
tHZBE
5
5
[9, 11]
BHE / BLE HIGH to High Z
25
25
[12]
WRITE CYCLE
tWC
tSCE
tAW
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WEPulse Width
tHA
tSA
0
0
tPWE
tBW
tSD
40
50
25
0
50
60
30
0
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[9, 11]
WE HIGH to Low Z[9]
tHD
tHZWE
20
25
tLZWE
5
10
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of
the specified IOL/IOH and 30 pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
10. If both byte enables are toggled together this value is 10ns
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/orBLE = VIL. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write..
5