62147BV
™
P relim inary
WCMA4016U1X
256K x 16 Static RAM
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
Features
• Low voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE1 and CE2 and OE fea-
tures
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description[1]
The WCMA4016U1X is a high-performance CMOS static
RAM organized as 262,144 words by 16 bits. This device
features advanced circuit design to provide ultra-low active
current and standby current. This is ideal for providing more
battery life in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99% when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this
datasheet for a complete description of read and write modes.
Logic Block Diagram
Pin
Configurations
FBGA (Top View)
1
2
4
3
5
6
A
A
A
2
CE
OE
BLE
0
1
2
A
B
C
DATA IN DRIVERS
A
A
4
I/O BHE
8
CE
I/O
I/O
0
3
A
9
A
A
8
7
6
A
A
6
I/O I/O
I/O
2
5
9
10
1
A
A
A
A
V
V
I/O
I/O
3
A
5
4
3
2
CC
D
E
F
SS
7
256K × 16
RAM Array
2048 × 2048
11
17
I/O – I/O
0
7
A
A
V
CC
NC
V
SS
I/O
I/O
16
12
4
I/O – I/O
A
8
15
A
A
1
0
A
A
15
I/O
I/O
I/O
I/O
6
14
13
5
14
A
A
G
H
I/O
I/O
NC
WE
13
12
15
7
COLUMN DECODER
A
A
9
A
A
NC
NC
10
11
8
BHE
WE
CE2
CE1
OE
BLE
Power -Down
Circuit
CE
CE
BHE
BLE
2
1
.
Weida Semiconductor, Inc.
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