Datasheet > WCMC1616V9X-FI70

WCMC1616V9X-FI70

更新时间： 2024-02-24 02:10:21

品牌	Logo	应用领域
韦达 - WEIDA		/
页数	文件大小	规格书
13页	214K
描述
1Mb x 16 Pseudo Static RAM

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技术参数
数据手册

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WCMC1616V9X-FI70 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

WCMC1616V9X-FI70 数据手册

WCMC1616V9X

ADVANCE INFORMATION

1Mb x 16 Pseudo Static RAM

(MoBL^®) in portable applications such as cellular telephones.

The device can be put into standby mode reducing power

consumption by more than 99% when deselected using CE

LOW, CE₂HIGH or both BHE and BLE are HIGH. The

input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when: deselected (CE HIGH, CE₂LOW

OE is deasserted HIGH), or during a write operation (Chip

Enabled and Write Enable WELOW). The device also has an

automatic power-down feature that significantly reduces

power consumption by 99% when addresses are not toggling

even when the chip is selected (Chip Enable CE LOW, CE₂

HIGH and both BHE and BLE are LOW). Reading from the

device is accomplished by asserting the Chip Enables (CE

LOW and CE₂HIGH) and Output Enable (OE) LOW while

forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)

is LOW, then data from the memory location specified by the

address pins will appear on I/O₀to I/O₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on I/O₈to

I/O₁₅. See the Truth Table for a complete description of read

and write modes.

Features

• 1T Cell, PSRAM Architecture

• High speed: 70 ns

• Wide Voltage range:

—V_CCrange: 2.7V to 3.3V

• Low active power

—Typical active current: 2 mA @ f = 1 MHz

—Typical active current: 13 mA @ f = f_MAX

• Low standby power

• Automatic power-down when deselected

Functional Description^[1]

The WCMC1616V9X is a high-performance CMOS pseudo

static RAMs (PSRAM) organized as 1M words by 16 bits that

supports an asynchronous memory interface. This device

features advanced circuit design to provide ultra-low active

current. This is ideal for providing More Battery Life^TM

Logic Block Diagram

DATA IN DRIVERS

1M x 16

RAM Array

I/O –I/O

COLUMN DECODER

BHE

BLE

Power -Down

Circuit

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

WeidaSemiconductor, Inc.

Document #: 38-14027 Rev. **

Revised August 22, 2001

12 3 4 5 6 7...13

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