WCMA4008C1X
512K x 8 Static RAM
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Features
• Voltage Range
— 4.5V–5.5V
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A18).
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = fmax
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the con-
tents of the memory location specified by the address pins will
appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The WCMA4008C1X is a high-performance CMOS static
RAM organized as 512K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE), an active
The WCMA4008C1X is available in a standard 32-pin
450-mil-wide body width SOIC.
Logic Block Diagram
Pin
Configuration
Top View
SOIC
VCC
A15
A18
A17
A16
32
31
30
1
2
3
4
5
6
7
I/O
I/O
I/O
0
INPUT BUFFER
A14
A12
A7
A6
1
2
29
28
27
26
A
0
WE
A13
A8
A
1
4
A
A5
A9
A
6
5
25
24
23
22
21
A
A4
A3
A2
8
9
10
11
12
13
A11
I/O
I/O
I/O
I/O
3
4
5
512 x 256 x 8
ARRAY
A
7
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
A
12
A1
A
14
A
A0
I/O0
16
A
17
20
19
18
I/O1
I/O2
GND
14
15
16
6
7
POWER
DOWN
17 I/O3
COLUMN
DECODER
CE
I/O
WE
OE