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WCMA1008U1X-SF70 PDF预览

WCMA1008U1X-SF70

更新时间: 2024-01-14 09:32:15
品牌 Logo 应用领域
韦达 - WEIDA /
页数 文件大小 规格书
12页 235K
描述
128K x 8 Static RAM

WCMA1008U1X-SF70 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

WCMA1008U1X-SF70 数据手册

 浏览型号WCMA1008U1X-SF70的Datasheet PDF文件第2页浏览型号WCMA1008U1X-SF70的Datasheet PDF文件第3页浏览型号WCMA1008U1X-SF70的Datasheet PDF文件第4页浏览型号WCMA1008U1X-SF70的Datasheet PDF文件第6页浏览型号WCMA1008U1X-SF70的Datasheet PDF文件第7页浏览型号WCMA1008U1X-SF70的Datasheet PDF文件第8页 
WCMA1008U1X  
Switching Characteristics Over the Operating Range[5]  
WCMA1008U1X-55 WCMA1008U1X-70  
Parameter  
READ CYCLE  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
tRC  
Read Cycle Time  
55  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
55  
70  
tOHA  
Data Hold from Address Change  
CE1 LOW and CE2 HIGH to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z[6]  
OE HIGH to High Z[6, 7]  
CE1 LOW and CE2 HIGH to Low Z[6]  
CE1 HIGH or CE2 LOW to High Z[6, 7]  
CE1 LOW and CE2 HIGH to Power-Up  
CE1 HIGH or CE2 LOW to Power-Down  
5
10  
tACE  
55  
20  
70  
35  
tDOE  
tLZOE  
10  
10  
0
10  
10  
0
tHZOE  
20  
20  
55  
25  
25  
70  
tLZCE  
tHZCE  
tPU  
tPD  
WRITE CYCLE[8,]  
tWC  
tSCE  
tAW  
Write Cycle Time  
55  
45  
45  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE1 LOW and CE2 HIGH to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
0
tPWE  
tSD  
45  
25  
0
55  
30  
0
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High Z[6, 7]  
WE HIGH to Low Z[6]  
tHD  
tHZWE  
20  
25  
tLZWE  
5
5
Notes:  
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the  
specified IOL/IOH and 30 pF load capacitance.  
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
7. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.  
8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these  
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.  
5

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