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W27E520S-90 PDF预览

W27E520S-90

更新时间: 2024-11-21 22:41:27
品牌 Logo 应用领域
华邦 - WINBOND 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
16页 232K
描述
64K X 8 ELECTRICALLY ERASABLE EPROM

W27E520S-90 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, SOP-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92最长访问时间:90 ns
命令用户界面:NO数据轮询:NO
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm内存密度:524288 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:20
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:2.67 mm最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.02 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30切换位:NO
宽度:7.5 mmBase Number Matches:1

W27E520S-90 数据手册

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W27E520  
´ 8 ELECTRICALLY ERASABLE EPROM  
64K  
GENERAL DESCRIPTION  
The W27E520 is a high speed, low power Electrically Erasable and Programmable Read Only  
´
Memory organized as 65,536 8 bits. It includes latches for the lower 8 address lines to multiplex  
with the 8 data lines. To cooperate with the MCU, this device could save the external TTL  
component, also cost and space. It requires only one supply in the range of 4.5V to 5.5V in normal  
read mode. The W27E520 provides an electrical chip erase function. It will be a great convenient  
when you need to change/update the contents in the device.  
FEATURES  
· High speed access time: 70/90 nS (max.)  
· Read operating current: 20 mA (max.)  
· Erase/Programming operating current  
· High Reliability CMOS Technology  
-
-
2K V ESD Protection  
200 mA Latchup Immunity  
· Fully static operation  
30 mA (max.)  
m
· Standby current: 100 A (max.)  
· All inputs and outputs directly TTL/CMOS  
compatible  
· Unregulated battery power supply range,  
4.5V to 5.5V  
· Three-state outputs  
· +13V erase and programming voltage  
· Available packages: 20-pin TSSOP and 20-pin  
SOP  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
ALE  
OE / V  
OUTPUT  
BUFFER  
1
A10  
A12  
A14  
ALE  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
A8  
CONTROL  
2
AD1  
AD3  
AD5  
AD7  
GND  
PP  
3
4
L
A
T
5
V
DD  
TSSOP  
Top View  
C
H
E
S
AD7 - AD0  
6
OE/VPP  
A15  
MEMORY  
ARRAY  
DECODER  
7
AD6  
AD4  
AD2  
AD0  
8
A15 - A8  
V
A13  
9
A11  
10  
DD  
A9  
GND  
1
VDD  
ALE  
A14  
A12  
A10  
A8  
OE/VPP  
A15  
20  
19  
18  
17  
2
PIN DESCRIPTION  
3
A13  
SYMBOL  
DESCRIPTION  
4
A11  
A9  
Address/Data Inputs/Outputs  
Address Inputs  
-
AD0 AD7  
5
SOP  
Top View  
16  
15  
14  
13  
12  
11  
6
-
A8 A15  
AD0  
7
AD1  
AD2  
AD4  
ALE  
Address Latch Enable  
Output Enable, Program/Erase  
Supply Voltage  
8
AD3  
AD5  
AD7  
PP  
OE  
/V  
9
AD6  
10  
GND  
DD  
V
Power Supply  
GND  
Ground  
Publication Release Date: September 2000  
Revision A2  
- 1 -  

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