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VNA7NV04D13TR PDF预览

VNA7NV04D13TR

更新时间: 2024-11-01 19:57:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动光电二极管接口集成电路
页数 文件大小 规格书
10页 70K
描述
2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO16, SO-16

VNA7NV04D13TR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SO-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
内置保护:TRANSIENT; OVER CURRENT; OVER VOLTAGE; THERMAL接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码:R-PDSO-G16长度:9.9 mm
功能数量:2端子数量:16
输出电流流向:SINK封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:1.75 mm表面贴装:YES
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

VNA7NV04D13TR 数据手册

 浏览型号VNA7NV04D13TR的Datasheet PDF文件第2页浏览型号VNA7NV04D13TR的Datasheet PDF文件第3页浏览型号VNA7NV04D13TR的Datasheet PDF文件第4页浏览型号VNA7NV04D13TR的Datasheet PDF文件第5页浏览型号VNA7NV04D13TR的Datasheet PDF文件第6页浏览型号VNA7NV04D13TR的Datasheet PDF文件第7页 
VNA7NV04D  
“OMNIFET II”:  
FULLY AUTOPROTECTED POWER MOSFETS  
TARGET SPECIFICATION  
TYPE  
RDS(on)  
Ilim  
Vclamp  
VNA7NV04D 60 m(*)  
6 A (*)  
40 V (*)  
(*) Per each device  
LINEAR CURRENT LIMITATION  
THERMAL SHUT DOWN  
SHORT CIRCUIT PROTECTIONS  
INTEGRATED CLAMP  
LOW CURRENT DRAWN FROM INPUT PINS  
DIAGNOSTIC FEEDBACK THROUGH INPUT  
PINS  
ESD PROTECTION  
DIRECT ACCESS TO THE GATE OF EACH  
SO-16 (DOUBLE ISLAND)  
POWER MOSFET (ANALOG DRIVING)  
COMPATIBLE WITH STANDARD POWER  
MOSFETS  
DESCRIPTION  
The VNA7NV04D is a device |formed by two|  
monolithic OMNIFET II chips housed in a  
standard SO-16 package with double island.  
MOSFETS from DC up to 50KHz applications.  
Built in thermal shutdown, linear current limitation  
and overvoltage clamp protect the chips in harsh  
environments.  
The  
OMNIFET  
II  
are  
designed  
in  
STMicroelectronics VIPower M0 Technology; they  
are intended for replacement of standard Power  
Fault feedback can be detected by monitoring the  
voltage at the input pins.  
BLOCK DIAGRAM  
DRAIN2  
DRAIN1  
OVERVOLTAGE  
CLAMP  
OVERVOLTAGE  
CLAMP  
INPUT1  
INPUT2  
GATE  
CONTROL  
GATE  
CONTROL  
LINEAR  
LINEAR  
CURRENT  
LIMITER  
CURRENT  
OVER  
TEMPERATURE  
OVER  
TEMPERATURE  
LIMITER  
SOURCE1 SOURCE2  
October 2000  
1/10  
1

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