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VNB20N07TR-E PDF预览

VNB20N07TR-E

更新时间: 2024-11-06 13:02:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 外围驱动器驱动程序和接口接口集成电路
页数 文件大小 规格书
13页 154K
描述
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VNB20N07TR-E 数据手册

 浏览型号VNB20N07TR-E的Datasheet PDF文件第2页浏览型号VNB20N07TR-E的Datasheet PDF文件第3页浏览型号VNB20N07TR-E的Datasheet PDF文件第4页浏览型号VNB20N07TR-E的Datasheet PDF文件第5页浏览型号VNB20N07TR-E的Datasheet PDF文件第6页浏览型号VNB20N07TR-E的Datasheet PDF文件第7页 
VNP20N07FI  
VNB20N07/VNV20N07  
”OMNIFET”:  
FULLY AUTOPROTECTED POWER MOSFET  
TYPE  
Vclamp  
RDS(on)  
Ilim  
VNP20N07FI  
VNB20N07  
VNV20N07  
70 V  
70 V  
70 V  
0.05 Ω  
0.05 Ω  
0.05 Ω  
20 A  
20 A  
20 A  
LINEAR CURRENT LIMITATION  
THERMAL SHUT DOWN  
SHORT CIRCUIT PROTECTION  
INTEGRATED CLAMP  
LOW CURRENT DRAWN FROM INPUT PIN  
DIAGNOSTIC FEEDBACK THROUGH INPUT  
PIN  
ISOWATT220  
3
2
1
ESD PROTECTION  
DIRECT ACCESS TO THE GATE OF THE  
POWER MOSFET (ANALOG DRIVING)  
COMPATIBLE WITH STANDARD POWER  
MOSFET  
10  
3
1
1
D2PAK  
TO-263  
PowerSO-10  
DESCRIPTION  
The VNP20N07FI, VNB20N07 and VNV20N07  
are  
monolithic  
devices  
made  
using  
STMicroelectronics VlPower M0 Technology,  
intended for replacement of standard power  
MOSFETS in DC to 50 KHz applications. Built-in  
thermal shut-down, linear current limitation and  
overvoltage clamp protect the chip in harsh  
enviroments.  
Fault feedback can be detected by monitoring the  
voltage at the input pin.  
BLOCK DIAGRAM ( )  
( ) PowerSO-10 Pin Configuration : INPUT = 6,7,8,9,10; SOURCE = 1,2,4,5; DRAIN = TAB  
June 1998  
1/13  

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