DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30500, 30500A
VR5000TM, VR5000ATM
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30500 (VR5000) and µPD30500A (VR5000A) are a high-performance, 64-/32-bit RISC (Reduced
InstructionSetComputer)typemicroprocessorsemployingtheRISCarchitecturedevelopedbyMIPSTM Technologies,
Inc.
The instructions of the VR5000 and VR5000A are compatible with those of the VR3000TM Series and VR4000TM
Series and higher, and completely compatible with those of the VR10000TM. Therefore, present applications can be
used as they are.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read
them before designing.
• VR5000, VR5000A User’s Manual (U11761E)
FEATURES
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Employs 64-bit MIPS-based RISC architecture
High-speed processing
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2-way super scalar 5-stage pipeline
5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (µPD30500)
7.0 SPECint95, 7.0 SPECfp95, 376 MIPS (µPD30500A)
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High-speed translation buffer mechanism (TLB) (48 entries)
Address space Physical: 36 bits, Virtual: 40 bits
Floating-point unit (FPU)
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Sum-of-products operation instruction supported
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Primary cache memory (instruction/data: 32 KB each)
Secondary cache controller
Maximum operating frequency Internal: 200 MHz (µPD30500), 266 MHz (µPD30500A)
External: 100 MHz
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Selectable external/internal multiple rate from twice to eight times
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Instruction set compatible with VR3000 and VR4000 Series and higher (conforms to MIPS I, II, III, and IV)
Supply voltage: 3.3 V ±5% (µPD30500)
Core: 2.4 V ±0.1 V (µPD30500A, @ 100 to 235 MHz),
2.5 V ±5% (µPD30500A, @ 236 to 250 MHz),
2.6 V ±0.1 V (µPD30500A, @ 251 to 266 MHz)
I/O: 3.3 V ±5% (µPD30500A)
Unless otherwise specified, the VR5000 (µPD30500) is treated as the representative model throughout this
document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark shows major revised points.
Document No. U12031EJ5V0DS00 (5th edition)
Date Published January 2001 N CP(K)
Printed in Japan
1997, 1999
©