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UPD30550AGD-300-WML-A PDF预览

UPD30550AGD-300-WML-A

更新时间: 2024-02-17 00:08:01
品牌 Logo 应用领域
日电电子 - NEC 时钟ISM频段外围集成电路
页数 文件大小 规格书
32页 402K
描述
RISC Microprocessor, 64-Bit, 300MHz, MOS, PQFP208, 28 X 28 MM, LEAD FREE, FINE PITCH, PLASTIC, QFP-208

UPD30550AGD-300-WML-A 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.61
地址总线宽度:64位大小:64
边界扫描:YES最大时钟频率:133 MHz
外部数据总线宽度:64格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-PQFP-G208
JESD-609代码:e6长度:28 mm
低功率模式:YES端子数量:208
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:3.8 mm速度:300 MHz
最大供电电压:1.575 V最小供电电压:1.425 V
标称供电电压:1.5 V表面贴装:YES
技术:MOS端子面层:TIN BISMUTH
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:10
宽度:28 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

UPD30550AGD-300-WML-A 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD30550A  
VR5500A, VR5532A  
64-/32-BIT MICROPROCESSOR  
DESCRIPTION  
The µPD30550AF2-300-NN1 and µPD30550AF2-400-NN1 (VR5500A), and µPD30550AGD-300-WML and  
µPD30550AGD-350-WML (VR5532A) are members of the VRTM Series of RISC (Reduced Instruction Set Computer)  
microprocessors. They are high-performance 64-/32-bit microprocessors that employ the RISC architecture  
developed by MIPSTM. The VR5500A uses a BGA package and provides a 300 MHz product and a 400 MHz product.  
The VR5532A uses a QFP package and provides a 300 MHz product and a 350 MHz product (please refer to  
ORDERING INFORMATION for details).  
The VR5500A allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using  
protocols compatible with the VR5000 Series and VR5432. The VR5532A does not include a system interface bus width  
selection function (the bus is fixed to 32 bits).  
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual  
before designing.  
VR5500A, VR5532A User’s Manual (U16677E/U16677J)  
FEATURES  
64-/32-bit address/data multiplexed bus  
Bus width selectable during resetNote  
MIPS 64-bit RISC architecture  
High-speed operation processing  
Two-way superscalar super pipeline  
[VR5500A]  
Bus protocol compatibility with existing products retained  
Maximum operating frequency  
[VR5500A]  
300 MHz product: 603 MIPS  
400 MHz product: 804 MIPS  
[VR5532A]  
300 MHz product: Internal 300 MHz, external 133 MHz  
400 MHz product: Internal 400 MHz, external 133 MHz  
[VR5532A]  
300 MHz product: 603 MIPS  
350 MHz product: 703 MIPS  
300 MHz product: Internal 300 MHz, external 100 MHz  
350 MHz product: Internal 350 MHz, external 100 MHz  
External/internal multiplication factor selectable from  
×2 to ×5.5 by increments of 0.5  
Conforms to MIPS I, II, III, and IV instruction sets. Also  
supports product-sum operation instruction, rotate  
instruction, register scan instruction, and instruction for  
low power mode.  
High-speed translation lookaside buffer (TLB)(48 entries)  
Address space  
Physical: 36 bits (64-bit bus selected)Note  
32 bits (32-bit bus selected)  
Virtual:  
40 bits (in 64-bit mode)  
31 bits (in 32-bit mode)  
On-chip floating-point unit (FPU)  
Supports sum-of-products instructions  
On-chip primary cache memory  
(instruction/data: 32 KB each)  
2-way set associative  
Supports hardware debug function (N-Wire)  
Supply voltage  
Core block: 1.5 V 5% (300 MHz product)  
1.5 V 5% (350 MHz product, VR5532A)  
1.6 to 1.7 V (400 MHz product, VR5500A)  
Supports line lock feature  
I/O block:  
3.3 V 5%, 2.5 V 5%  
Note VR5500A only.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. U16678EJ3V0DS00 (3rd edition)  
Date Published March 2004 NS CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
2003  
2001  

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