Datasheet > UPD30710RS-300

UPD30710RS-300

更新时间： 2024-01-10 08:47:02

品牌	Logo	应用领域
其他 - ETC		外围集成电路微处理器时钟
页数	文件大小	规格书
68页	265K
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Microprocessor

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UPD30710RS-300 数据手册

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD30700,30700L,30710

VR10000^TM, VR12000^TM

64-BIT MICROPROCESSORS

DESCRIPTION

The µPD30700 and 30700L (VR10000) and µPD30710 (VR12000) are new members of NEC’s VR series^TMRISC

(Reduced Instruction Set Computer) microprocessors. These new high-performance 64-bit microprocessors employ

a new RISC architecture developed by MIPS^TM, ANDES^TMarchitecture.

The V^R10000 and VR12000 are designed to be used in high-performance computers and achieve considerably

higher processing speed through the employment of a super scalar pipeline.

Remark ANDES: Architecture with Non-sequential Dynamic Execution Scheduling

The functions of these microprocessors are described in detail in the following manuals. Be sure to read these

manuals when designing systems.

V^R10000, VR12000 User’s Manual

: U10278E

VR5000^TM, VR10000 User’s Manual - Instruction : U12754E

FEATURES

MIPS 64-bit RISC architecture

Operating frequency

•

High-speed operation processing

<V^R10000>

Superscalarpipelineexecutingfiveinstructionsinparallel

• Internal: 250 MHz MAX.

• External: 250 MHz MAX.

• External/internal multiplication factor selectable from

1 to 4

<V^R10000>

• 14SPECint95, 23SPECfp95

<V^R12000>

• 17SPECint95, 27SPECfp95

<V^R12000>

Instruction set upward-compatible with VR4000^TM

• Internal: 300 MHz MAX.

• External: 150 MHz MAX.

• External/internal multiplication factor selectable from

2 to 10

•

VR4200^TM, and VR4400^TM(conforms to MIPS-I/II/III/IV)

High-speedtranslationlookasidebuffer(TLB)(64double

entries)

•

Address space Physical: 40 bits

Virtual: 44 bits

Multi-processor function

•

• Uptofourbusesofclusterconnectioncanbeconnected.

Floating-point unit (FPU)

Supply voltage

•

Primarycachememory(32Kbytesforeachofinstruction <VR10000>

and data, 2-way set associative)

Secondary cache memory interface

• 128-bit secondary cache interface

• SSRAMinterface(VR10000:250MHzMAX.,VR12000:

200 MHz MAX.)

VDD = 3.3 V ±0.165 V (µPD30700)

V^DD= 2.6 V ±0.1 V (µPD30700L)

•

VDD = 2.6 V ±0.1 V (µPD30710)

• Supports up to 16M bytes

Unless otherwise specified, the VR10000 is treated as the representative model throughout this document.

The information in this document is subject to change without notice.

Date No. U12703EJ1V0DS00 (1st edition)

Date Published June 1998 N CP(K)

Printed in Japan

1998

MIPS Technologies Inc.

12 3 4 5 6 7...68

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